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533 lines
16 KiB
533 lines
16 KiB
//===== Copyright © 1996-2005, Valve Corporation, All rights reserved. ======//
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//
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// Purpose: API-independent render state declarations
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//
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// $NoKeywords: $
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//
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//===========================================================================//
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#ifndef RENDERSTATE_H
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#define RENDERSTATE_H
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#ifdef _WIN32
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#pragma once
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#endif
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#include "tier1/interface.h"
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#include "tier1/generichash.h"
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#include "basetypes.h"
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#include "mathlib/mathlib.h"
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//-----------------------------------------------------------------------------
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// Handle to render state objects
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//-----------------------------------------------------------------------------
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DECLARE_POINTER_HANDLE( RsRasterizerStateHandle_t );
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#define RENDER_RASTERIZER_STATE_HANDLE_INVALID ( (RsRasterizerStateHandle_t)0 )
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DECLARE_POINTER_HANDLE( RsDepthStencilStateHandle_t );
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#define RENDER_DEPTH_STENCIL_STATE_HANDLE_INVALID ( (RsDepthStencilStateHandle_t)0 )
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DECLARE_POINTER_HANDLE( RsBlendStateHandle_t );
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#define RENDER_BLEND_STATE_HANDLE_INVALID ( (RsBlendStateHandle_t)0 )
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//-----------------------------------------------------------------------------
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// Packs a float4 color to ARGB 8-bit int color compatible with D3D9
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//-----------------------------------------------------------------------------
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FORCEINLINE uint32 PackFloat4ColorToUInt32( float flR, float flG, float flB, float flA )
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{
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uint32 nR, nG, nB, nA;
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nR = uint32( flR * 255.0f );
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nG = uint32( flG * 255.0f );
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nB = uint32( flB * 255.0f );
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nA = uint32( flA * 255.0f );
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return ( ( nA & 0xFF ) << 24 ) | ( ( nR & 0xFF ) << 16 ) | ( ( nG & 0xFF ) << 8 ) | ( ( nB & 0xFF ) );
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}
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//-----------------------------------------------------------------------------
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// Packs a float4 color to ARGB 8-bit int color compatible with D3D9, clamping the floats to [0, 1]
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//-----------------------------------------------------------------------------
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FORCEINLINE uint32 ClampAndPackFloat4ColorToUInt32( float flR, float flG, float flB, float flA )
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{
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uint32 nR, nG, nB, nA;
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nR = uint32( clamp( flR, 0.0f, 1.0f ) * 255.0f );
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nG = uint32( clamp( flG, 0.0f, 1.0f ) * 255.0f );
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nB = uint32( clamp( flB, 0.0f, 1.0f ) * 255.0f );
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nA = uint32( clamp( flA, 0.0f, 1.0f ) * 255.0f );
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return ( ( nA & 0xFF ) << 24 ) | ( ( nR & 0xFF ) << 16 ) | ( ( nG & 0xFF ) << 8 ) | ( ( nB & 0xFF ) );
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}
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//-----------------------------------------------------------------------------
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// Unpacks an ARGB 8-bit int color to 4 floats
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//-----------------------------------------------------------------------------
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FORCEINLINE void UnpackUint32ColorToFloat4( uint32 nPackedColor, float* pflR, float* pflG, float* pflB, float* pflA )
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{
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uint32 nR, nG, nB, nA;
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nR = ( nPackedColor >> 16 ) & 0xFF;
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nG = ( nPackedColor >> 8 ) & 0xFF;
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nB = ( nPackedColor ) & 0xFF;
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nA = ( nPackedColor >> 24 ) & 0xFF;
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*pflR = nR * 255.0f;
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*pflG = nG * 255.0f;
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*pflB = nB * 255.0f;
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*pflA = nA * 255.0f;
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}
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enum RsCullMode_t
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{
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RS_CULL_NONE = 0,
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RS_CULL_BACK = 1,
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RS_CULL_FRONT = 2
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};
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enum RsFillMode_t
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{
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RS_FILL_SOLID = 0,
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RS_FILL_WIREFRAME = 1
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};
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enum RsComparison_t
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{
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RS_CMP_NEVER = 0,
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RS_CMP_LESS = 1,
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RS_CMP_EQUAL = 2,
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RS_CMP_LESS_EQUAL = 3,
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RS_CMP_GREATER = 4,
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RS_CMP_NOT_EQUAL = 5,
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RS_CMP_GREATER_EQUAL = 6,
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RS_CMP_ALWAYS = 7
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};
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enum RsStencilOp_t
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{
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RS_STENCIL_OP_KEEP = 0,
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RS_STENCIL_OP_ZERO = 1,
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RS_STENCIL_OP_REPLACE = 2,
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RS_STENCIL_OP_INCR_SAT = 3,
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RS_STENCIL_OP_DECR_SAT = 4,
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RS_STENCIL_OP_INVERT = 5,
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RS_STENCIL_OP_INCR = 6,
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RS_STENCIL_OP_DECR = 7
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};
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enum RsHiStencilComparison360_t
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{
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RS_HI_STENCIL_CMP_EQUAL = 0,
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RS_HI_STENCIL_CMP_NOT_EQUAL = 1
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};
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enum RsHiZMode360_t
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{
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RS_HI_Z_AUTOMATIC = 0,
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RS_HI_Z_DISABLE = 1,
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RS_HI_Z_ENABLE = 2
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};
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enum RsBlendOp_t
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{
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RS_BLEND_OP_ADD = 0,
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RS_BLEND_OP_SUBTRACT = 1,
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RS_BLEND_OP_REV_SUBTRACT = 2,
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RS_BLEND_OP_MIN = 3,
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RS_BLEND_OP_MAX = 4
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};
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enum RsBlendMode_t
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{
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RS_BLEND_MODE_ZERO = 0,
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RS_BLEND_MODE_ONE = 1,
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RS_BLEND_MODE_SRC_COLOR = 2,
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RS_BLEND_MODE_INV_SRC_COLOR = 3,
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RS_BLEND_MODE_SRC_ALPHA = 4,
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RS_BLEND_MODE_INV_SRC_ALPHA = 5,
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RS_BLEND_MODE_DEST_ALPHA = 6,
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RS_BLEND_MODE_INV_DEST_ALPHA = 7,
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RS_BLEND_MODE_DEST_COLOR = 8,
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RS_BLEND_MODE_INV_DEST_COLOR = 9,
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RS_BLEND_MODE_SRC_ALPHA_SAT = 10,
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RS_BLEND_MODE_BLEND_FACTOR = 11,
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RS_BLEND_MODE_INV_BLEND_FACTOR = 12
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};
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enum RsColorWriteEnableBits_t
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{
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RS_COLOR_WRITE_ENABLE_R = 0x1,
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RS_COLOR_WRITE_ENABLE_G = 0x2,
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RS_COLOR_WRITE_ENABLE_B = 0x4,
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RS_COLOR_WRITE_ENABLE_A = 0x8,
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RS_COLOR_WRITE_ENABLE_ALL = RS_COLOR_WRITE_ENABLE_R | RS_COLOR_WRITE_ENABLE_G | RS_COLOR_WRITE_ENABLE_B | RS_COLOR_WRITE_ENABLE_A
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};
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enum
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{
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RS_MAX_RENDER_TARGETS = 8
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};
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//-----------------------------------------------------------------------------
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struct RsRasterizerStateDesc_t
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{
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RsFillMode_t m_nFillMode;
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RsCullMode_t m_nCullMode;
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bool m_bDepthClipEnable;
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bool m_bMultisampleEnable;
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int32 m_nDepthBias; // TODO: make this a float?
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float32 m_flDepthBiasClamp;
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float32 m_flSlopeScaledDepthBias;
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/* Not exposing these DX11 states
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BOOL FrontCounterClockwise;
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BOOL ScissorEnable;
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BOOL AntialiasedLineEnable;
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This needs to be passed in explicitly when setting the blend state op:
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uint32 multisamplemask;
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*/
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FORCEINLINE uint32 HashValue() const
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{
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// TODO: Optimize this
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return HashItem( *this );
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}
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FORCEINLINE bool operator==( RsRasterizerStateDesc_t const &state ) const
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{
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return memcmp( this, &state, sizeof( RsRasterizerStateDesc_t ) ) == 0;
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}
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};
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//-----------------------------------------------------------------------------
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struct RsDepthStencilStateDesc_t
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{
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bool m_bDepthTestEnable;
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bool m_bDepthWriteEnable;
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RsComparison_t m_depthFunc;
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RsHiZMode360_t m_hiZEnable360;
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RsHiZMode360_t m_hiZWriteEnable360;
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bool m_bStencilEnable;
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uint8 m_nStencilReadMask;
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uint8 m_nStencilWriteMask;
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RsStencilOp_t m_frontStencilFailOp;
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RsStencilOp_t m_frontStencilDepthFailOp;
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RsStencilOp_t m_frontStencilPassOp;
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RsComparison_t m_frontStencilFunc;
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RsStencilOp_t m_backStencilFailOp;
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RsStencilOp_t m_backStencilDepthFailOp;
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RsStencilOp_t m_backStencilPassOp;
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RsComparison_t m_backStencilFunc;
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bool m_bHiStencilEnable360;
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bool m_bHiStencilWriteEnable360;
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RsHiStencilComparison360_t m_hiStencilFunc360;
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uint8 m_nHiStencilRef360;
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// Stencil ref not part of this, it's set explicitly when binding DS state block
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// TODO: Figure out if I should pull the 360 HiStencil ref out too.
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FORCEINLINE uint32 HashValue() const
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{
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// TODO: Optimize this
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return HashItem( *this );
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}
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FORCEINLINE bool operator==( RsDepthStencilStateDesc_t const &state ) const
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{
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return memcmp( this, &state, sizeof( RsDepthStencilStateDesc_t ) ) == 0;
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}
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};
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//-----------------------------------------------------------------------------
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struct RsBlendStateDesc_t
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{
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bool m_bAlphaToCoverageEnable;
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bool m_bIndependentBlendEnable;
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bool m_bHighPrecisionBlendEnable360;
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bool m_bBlendEnable[RS_MAX_RENDER_TARGETS];
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RsBlendMode_t m_srcBlend[RS_MAX_RENDER_TARGETS];
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RsBlendMode_t m_destBlend[RS_MAX_RENDER_TARGETS];
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RsBlendOp_t m_blendOp[RS_MAX_RENDER_TARGETS];
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RsBlendMode_t m_srcBlendAlpha[RS_MAX_RENDER_TARGETS];
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RsBlendMode_t m_destBlendAlpha[RS_MAX_RENDER_TARGETS];
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RsBlendOp_t m_blendOpAlpha[RS_MAX_RENDER_TARGETS];
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uint8 m_nRenderTargetWriteMask[RS_MAX_RENDER_TARGETS];
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FORCEINLINE uint32 HashValue() const
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{
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// TODO: Optimize this
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return HashItem( *this );
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}
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FORCEINLINE bool operator==( RsBlendStateDesc_t const &state ) const
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{
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return memcmp( this, &state, sizeof( RsBlendStateDesc_t ) ) == 0;
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}
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};
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enum RsFilter_t
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{
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RS_FILTER_MIN_MAG_MIP_POINT = 0,
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RS_FILTER_MIN_MAG_POINT_MIP_LINEAR = 0x1,
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RS_FILTER_MIN_POINT_MAG_LINEAR_MIP_POINT = 0x4,
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RS_FILTER_MIN_POINT_MAG_MIP_LINEAR = 0x5,
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RS_FILTER_MIN_LINEAR_MAG_MIP_POINT = 0x10,
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RS_FILTER_MIN_LINEAR_MAG_POINT_MIP_LINEAR = 0x11,
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RS_FILTER_MIN_MAG_LINEAR_MIP_POINT = 0x14,
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RS_FILTER_MIN_MAG_MIP_LINEAR = 0x15,
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RS_FILTER_ANISOTROPIC = 0x55,
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RS_FILTER_COMPARISON_MIN_MAG_MIP_POINT = 0x80,
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RS_FILTER_COMPARISON_MIN_MAG_POINT_MIP_LINEAR = 0x81,
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RS_FILTER_COMPARISON_MIN_POINT_MAG_LINEAR_MIP_POINT = 0x84,
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RS_FILTER_COMPARISON_MIN_POINT_MAG_MIP_LINEAR = 0x85,
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RS_FILTER_COMPARISON_MIN_LINEAR_MAG_MIP_POINT = 0x90,
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RS_FILTER_COMPARISON_MIN_LINEAR_MAG_POINT_MIP_LINEAR = 0x91,
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RS_FILTER_COMPARISON_MIN_MAG_LINEAR_MIP_POINT = 0x94,
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RS_FILTER_COMPARISON_MIN_MAG_MIP_LINEAR = 0x95,
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RS_FILTER_COMPARISON_ANISOTROPIC = 0xd5
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};
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enum RsFilterType_t
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{
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RS_FILTER_TYPE_POINT = 0,
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RS_FILTER_TYPE_LINEAR = 1
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};
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FORCEINLINE RsFilter_t RsEncodeBasicTextureFilter( RsFilterType_t minFilter, RsFilterType_t magFilter, RsFilterType_t mipFilter, bool bComparison )
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{
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return static_cast< RsFilter_t >( ( bComparison ? 0x80 : 0 ) | ( ( minFilter & 0x3 ) << 4 ) | ( ( magFilter & 0x3 ) << 2 ) | ( mipFilter & 0x3 ) );
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}
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FORCEINLINE RsFilter_t RsEncodeAnisoTextureFilter( bool bComparison )
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{
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return RsEncodeBasicTextureFilter( RS_FILTER_TYPE_LINEAR, RS_FILTER_TYPE_LINEAR, RS_FILTER_TYPE_LINEAR, bComparison );
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}
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FORCEINLINE RsFilterType_t RsGetTextureMinFilterType( RsFilter_t filter )
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{
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return static_cast< RsFilterType_t >( 0x3 & ( filter >> 4 ) );
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}
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FORCEINLINE RsFilterType_t RsGetTextureMagFilterType( RsFilter_t filter )
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{
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return static_cast< RsFilterType_t >( 0x3 & ( filter >> 2 ) );
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}
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FORCEINLINE RsFilterType_t RsGetTextureMipFilterType( RsFilter_t filter )
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{
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return static_cast< RsFilterType_t >( 0x3 & filter );
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}
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FORCEINLINE bool RsIsComparisonTextureFilter( RsFilter_t filter )
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{
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return ( filter & 0x80 ) != 0;
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}
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FORCEINLINE bool RsIsAnisoTextureFilter( RsFilter_t filter )
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{
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return static_cast< RsFilter_t >( filter & ~0x80 ) == RS_FILTER_ANISOTROPIC;
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}
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enum RsTextureAddressMode_t
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{
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RS_TEXTURE_ADDRESS_WRAP = 0,
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RS_TEXTURE_ADDRESS_MIRROR = 1,
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RS_TEXTURE_ADDRESS_CLAMP = 2,
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RS_TEXTURE_ADDRESS_BORDER = 3,
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RS_TEXTURE_ADDRESS_MIRROR_ONCE = 4
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};
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//-----------------------------------------------------------------------------
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class CSamplerStateDesc
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{
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public:
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explicit CSamplerStateDesc( RsFilter_t filter = RS_FILTER_MIN_MAG_MIP_LINEAR,
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RsTextureAddressMode_t addressU = RS_TEXTURE_ADDRESS_WRAP,
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RsTextureAddressMode_t addressV = RS_TEXTURE_ADDRESS_WRAP,
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RsTextureAddressMode_t addressW = RS_TEXTURE_ADDRESS_WRAP,
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float32 flMipLodBias = 0.0f,
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uint32 nMaxAniso = 16,
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RsComparison_t comparisonFunc = RS_CMP_LESS,
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uint32 nMinLod = 0,
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uint32 nMaxLod = 16,
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bool bSrgbFetch = false,
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bool bFetch4 = false )
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{
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SetFilterMode( filter );
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SetTextureAddressModeU( addressU );
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SetTextureAddressModeV( addressU );
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SetTextureAddressModeW( addressU );
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SetMipLodBias( flMipLodBias );
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SetMaxAnisotropy( nMaxAniso );
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SetComparisonFunc( comparisonFunc );
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SetMinMaxLod( nMinLod, nMaxLod );
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SetSrgbFetchEnabled( bSrgbFetch );
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SetFetch4Enabled( bFetch4 );
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float32 flZeros[4] = { 0.0f, 0.0f, 0.0f, 0.0f };
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SetBorderColor( flZeros );
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m_nPad = 0;
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}
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FORCEINLINE RsFilter_t GetFilterMode() const { return static_cast< RsFilter_t >( m_nFilterMode ); }
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FORCEINLINE void SetFilterMode( RsFilter_t filter ) { m_nFilterMode = filter; }
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FORCEINLINE RsTextureAddressMode_t GetTextureAddressModeU() const { return static_cast< RsTextureAddressMode_t >( m_nAddressU ); }
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FORCEINLINE RsTextureAddressMode_t GetTextureAddressModeV() const { return static_cast< RsTextureAddressMode_t >( m_nAddressV ); }
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FORCEINLINE RsTextureAddressMode_t GetTextureAddressModeW() const { return static_cast< RsTextureAddressMode_t >( m_nAddressW ); }
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FORCEINLINE void SetTextureAddressModeU( RsTextureAddressMode_t addressMode ) { m_nAddressU = addressMode; }
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FORCEINLINE void SetTextureAddressModeV( RsTextureAddressMode_t addressMode ) { m_nAddressV = addressMode; }
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FORCEINLINE void SetTextureAddressModeW( RsTextureAddressMode_t addressMode ) { m_nAddressW = addressMode; }
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FORCEINLINE float32 GetMipLodBias() const
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{
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return float32( m_nMipLodBias ) / 16.0f * ( m_nMipLodBiasSign ? -1.0f : 1.0f );
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}
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FORCEINLINE void SetMipLodBias( float32 flBias )
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{
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m_nMipLodBias = int( fabsf( flBias ) * 16.0f );
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m_nMipLodBiasSign = ( flBias >= 0.0f ) ? 0 : 1;
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}
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FORCEINLINE uint32 GetMaxAnisotropy() const { return 1 << m_nAnisoExp; }
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FORCEINLINE void SetMaxAnisotropy( uint32 nMaxAniso )
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{
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uint32 nAnisoExp = uint32( FastLog2( MAX( nMaxAniso, 1 ) ) );
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m_nAnisoExp = MIN( nAnisoExp, 7 );
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}
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FORCEINLINE RsComparison_t GetComparisonFunc() const { return static_cast< RsComparison_t >( m_nComparisonFunc ); }
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FORCEINLINE void SetComparisonFunc( RsComparison_t compFunc ) { m_nComparisonFunc = compFunc; }
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FORCEINLINE void SetBorderColor( const float32 *pBorderColor )
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{
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m_nBorderColor8Bit = ClampAndPackFloat4ColorToUInt32( pBorderColor[0], pBorderColor[1], pBorderColor[2], pBorderColor[3] );
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}
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FORCEINLINE void GetBorderColor( float32 *pBorderColorOut ) const
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{
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UnpackUint32ColorToFloat4( m_nBorderColor8Bit, pBorderColorOut, pBorderColorOut + 1, pBorderColorOut + 2, pBorderColorOut + 3 );
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}
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FORCEINLINE uint32 GetBorderColor32Bit() const
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{
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return m_nBorderColor8Bit;
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}
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FORCEINLINE void GetMinMaxLod( uint32 *pMinLodOut, uint32 *pMaxLodOut ) const
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{
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*pMinLodOut = m_nMinLod;
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*pMaxLodOut = m_nMaxLod;
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}
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FORCEINLINE uint32 GetMinLod() const
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{
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return m_nMinLod;
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}
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FORCEINLINE uint32 GetMaxLod() const
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{
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return m_nMaxLod;
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}
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FORCEINLINE void SetMinMaxLod( uint32 nMinLod, uint32 nMaxLod )
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{
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m_nMinLod = MIN( 15, nMinLod );
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m_nMaxLod = MIN( 15, nMaxLod );
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}
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FORCEINLINE void SetMinLod( uint32 nMinLod )
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{
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m_nMinLod = MIN( 15, nMinLod );
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}
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FORCEINLINE void SetMaxLod( uint32 nMaxLod )
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{
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m_nMaxLod = MIN( 15, nMaxLod );
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}
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bool GetFetch4Enabled() const { return m_nFetch4Enable ? true : false; }
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void SetFetch4Enabled( bool bEnable ) { m_nFetch4Enable = bEnable; }
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bool GetSrgbFetchEnabled() const { return m_nSrgbFetchEnable ? true : false; }
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void SetSrgbFetchEnabled( bool bEnable ) { m_nSrgbFetchEnable = bEnable; }
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|
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FORCEINLINE uint32 HashValue( void ) const
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|
{
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|
COMPILE_TIME_ASSERT( sizeof( CSamplerStateDesc ) == 12 );
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|
return Hash12( this );
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|
}
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|
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FORCEINLINE bool operator==( CSamplerStateDesc const &state ) const
|
|
{
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|
return memcmp( this, &state, sizeof( CSamplerStateDesc ) ) == 0;
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|
}
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|
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|
private:
|
|
|
|
// 32 bits
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|
uint32 m_nFilterMode : 8;
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|
uint32 m_nMipLodBias : 8; // 4.4 fixed point
|
|
uint32 m_nMipLodBiasSign : 1;
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|
uint32 m_nAddressU : 3;
|
|
uint32 m_nAddressV : 3;
|
|
uint32 m_nAddressW : 3;
|
|
uint32 m_nAnisoExp : 3;
|
|
uint32 m_nComparisonFunc : 3;
|
|
|
|
// 32 bits
|
|
uint32 m_nBorderColor8Bit;
|
|
|
|
// 32 bits (18 bits available for extension
|
|
uint32 m_nMinLod : 6; // TODO: Either make them fixed-point, or kick them out of the state block alltogether
|
|
uint32 m_nMaxLod : 6;
|
|
uint32 m_nFetch4Enable : 1;
|
|
uint32 m_nSrgbFetchEnable : 1;
|
|
uint32 m_nPad : 18;
|
|
};
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
// Enums for builtin state objects
|
|
//-----------------------------------------------------------------------------
|
|
enum RenderCullMode_t
|
|
{
|
|
RENDER_CULLMODE_CULL_BACKFACING = 0, // this culls polygons with clockwise winding
|
|
RENDER_CULLMODE_CULL_FRONTFACING = 1, // this culls polygons with counterclockwise winding
|
|
RENDER_CULLMODE_CULL_NONE = 2, // no culling
|
|
};
|
|
|
|
enum RenderZBufferMode_t
|
|
{
|
|
RENDER_ZBUFFER_NONE = 0,
|
|
RENDER_ZBUFFER_ZTEST_AND_WRITE,
|
|
RENDER_ZBUFFER_ZTEST_NO_WRITE,
|
|
RENDER_ZBUFFER_ZTEST_GREATER_NO_WRITE,
|
|
RENDER_ZBUFFER_ZTEST_EQUAL_NO_WRITE,
|
|
|
|
// Stencil modes
|
|
RENDER_ZBUFFER_NONE_STENCIL_TEST_NOTEQUAL,
|
|
RENDER_ZBUFFER_ZTEST_AND_WRITE_STENCIL_SET1,
|
|
RENDER_ZBUFFER_ZTEST_NO_WRITE_STENCIL_TEST_NOTEQUAL_SET0,
|
|
RENDER_ZBUFFER_ZTEST_GREATER_NO_WRITE_STENCIL_TEST_NOTEQUAL_SET0,
|
|
|
|
RENDER_ZBUFFER_NUM_BUILTIN_MODES
|
|
};
|
|
|
|
enum RenderBlendMode_t
|
|
{
|
|
RENDER_BLEND_NONE = 0,
|
|
RENDER_BLEND_NOPIXELWRITE = 1,
|
|
RENDER_BLEND_RGBAPIXELWRITE,
|
|
RENDER_BLEND_ALPHABLENDING,
|
|
RENDER_BLEND_ADDITIVE_ON_ALPHA,
|
|
|
|
RENDER_NUM_BUILTIN_BLENDSTATES
|
|
};
|
|
|
|
#endif // RENDERSTATE_H
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