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84 lines
3.3 KiB
84 lines
3.3 KiB
//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the subtarget options of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
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#define LLVM_TARGET_TARGETSUBTARGETINFO_H
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class MachineFunction;
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class MachineInstr;
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class SDep;
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class SUnit;
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class TargetRegisterClass;
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class TargetSchedModel;
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template <typename T> class SmallVectorImpl;
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//===----------------------------------------------------------------------===//
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///
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/// TargetSubtargetInfo - Generic base class for all target subtargets. All
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/// Target-specific options that control code generation and printing should
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/// be exposed through a TargetSubtargetInfo-derived class.
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///
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class TargetSubtargetInfo : public MCSubtargetInfo {
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TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
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void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
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protected: // Can only create subclasses...
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TargetSubtargetInfo();
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public:
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// AntiDepBreakMode - Type of anti-dependence breaking that should
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// be performed before post-RA scheduling.
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typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
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typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector;
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virtual ~TargetSubtargetInfo();
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/// Resolve a SchedClass at runtime, where SchedClass identifies an
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/// MCSchedClassDesc with the isVariant property. This may return the ID of
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/// another variant SchedClass, but repeated invocation must quickly terminate
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/// in a nonvariant SchedClass.
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virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,
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const TargetSchedModel* SchedModel) const {
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return 0;
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}
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/// \brief True if the subtarget should run MachineScheduler after aggressive
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/// coalescing.
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///
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/// This currently replaces the SelectionDAG scheduler with the "source" order
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/// scheduler. It does not yet disable the postRA scheduler.
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virtual bool enableMachineScheduler() const;
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// enablePostRAScheduler - If the target can benefit from post-regalloc
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// scheduling and the specified optimization level meets the requirement
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// return true to enable post-register-allocation scheduling. In
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// CriticalPathRCs return any register classes that should only be broken
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// if on the critical path.
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virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const;
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// adjustSchedDependency - Perform target specific adjustments to
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// the latency of a schedule dependency.
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virtual void adjustSchedDependency(SUnit *def, SUnit *use,
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SDep& dep) const { }
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/// \brief Reset the features for the subtarget.
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virtual void resetSubtargetFeatures(const MachineFunction *MF) { }
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};
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} // End llvm namespace
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#endif
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