Windows NT 4.0 source code leak
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  1. /*++
  2. Copyright (c) 1993 Digital Equipment Corporation
  3. Module Name:
  4. ebsysint.c
  5. Abstract:
  6. This module implements the HAL enable/disable system interrupt, and
  7. request interprocessor interrupt routines for a Low Cost Alpha (LCA)
  8. based system.
  9. Originally taken from JENSEN hal code.
  10. Author:
  11. Wim Colgate 26-Oct-1993
  12. Environment:
  13. Kernel mode
  14. Revision History:
  15. Dick Bissen [DEC] 12-May-1994
  16. Removed all support of the EB66 pass1 module from the code.
  17. --*/
  18. #include "halp.h"
  19. #include "eb66def.h"
  20. #include "axp21064.h"
  21. //
  22. // Define reference to the builtin device interrupt enables.
  23. //
  24. extern USHORT HalpBuiltinInterruptEnable;
  25. extern BOOLEAN bMustang;
  26. VOID
  27. HalDisableSystemInterrupt (
  28. IN ULONG Vector,
  29. IN KIRQL Irql
  30. )
  31. /*++
  32. Routine Description:
  33. This routine disables the specified system interrupt.
  34. Arguments:
  35. Vector - Supplies the vector of the system interrupt that is disabled.
  36. Irql - Supplies the IRQL of the interrupting source.
  37. Return Value:
  38. None.
  39. --*/
  40. {
  41. ULONG Irq;
  42. KIRQL OldIrql;
  43. //
  44. // Raise IRQL to the highest level.
  45. //
  46. KeRaiseIrql(HIGH_LEVEL, &OldIrql);
  47. //
  48. // If the vector number is within the range of the ISA interrupts, then
  49. // disable the ISA interrrupt.
  50. //
  51. if (Vector >= ISA_VECTORS &&
  52. Vector < MAXIMUM_ISA_VECTOR &&
  53. Irql == ISA_DEVICE_LEVEL) {
  54. HalpDisableSioInterrupt(Vector);
  55. }
  56. //
  57. // If the vector number is within the range of the PCI interrupts, then
  58. // disable the PCI interrrupt.
  59. if (Vector >= PCI_VECTORS &&
  60. Vector < MAXIMUM_PCI_VECTOR &&
  61. Irql == PCI_DEVICE_LEVEL) {
  62. HalpDisablePCIInterrupt(Vector);
  63. }
  64. //
  65. // If the vector is a performance counter vector or one of the internal
  66. // device vectors (serial and keyboard/mouse for LCA) then disable the
  67. // interrupt.
  68. //
  69. switch (Vector) {
  70. //
  71. // Performance counter 0 interrupt (internal to 21064)
  72. //
  73. case PC0_VECTOR:
  74. case PC0_SECONDARY_VECTOR:
  75. HalpDisable21064PerformanceInterrupt( Vector );
  76. break;
  77. //
  78. // Performance counter 1 interrupt (internal to 21064)
  79. //
  80. case PC1_VECTOR:
  81. case PC1_SECONDARY_VECTOR:
  82. HalpDisable21064PerformanceInterrupt( Vector );
  83. break;
  84. } //end switch Vector
  85. //
  86. // Lower IRQL to the previous level.
  87. //
  88. KeLowerIrql(OldIrql);
  89. return;
  90. }
  91. BOOLEAN
  92. HalEnableSystemInterrupt (
  93. IN ULONG Vector,
  94. IN KIRQL Irql,
  95. IN KINTERRUPT_MODE InterruptMode
  96. )
  97. /*++
  98. Routine Description:
  99. This routine enables the specified system interrupt.
  100. Arguments:
  101. Vector - Supplies the vector of the system interrupt that is enabled.
  102. Irql - Supplies the IRQL of the interrupting source.
  103. InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
  104. Latched.
  105. Return Value:
  106. TRUE if the system interrupt was enabled
  107. --*/
  108. {
  109. BOOLEAN Enabled = FALSE;
  110. ULONG Irq;
  111. KIRQL OldIrql;
  112. //
  113. // Raise IRQL to the highest level.
  114. //
  115. KeRaiseIrql(HIGH_LEVEL, &OldIrql);
  116. //
  117. // If the vector number is within the range of the ISA interrupts, then
  118. // enable the ISA interrrupt. It must be latched.
  119. //
  120. if (Vector >= ISA_VECTORS &&
  121. Vector < MAXIMUM_ISA_VECTOR &&
  122. Irql == ISA_DEVICE_LEVEL) {
  123. HalpEnableSioInterrupt( Vector, InterruptMode );
  124. Enabled = TRUE;
  125. }
  126. //
  127. // If the vector number is within the range of the PCI interrupts, then
  128. // enable the PCI interrrupt. PCI interrupts must be LevelSensitve.
  129. // (PCI Spec. 2.2.6)
  130. //
  131. if (Vector >= PCI_VECTORS &&
  132. Vector < MAXIMUM_PCI_VECTOR &&
  133. Irql == PCI_DEVICE_LEVEL &&
  134. InterruptMode == LevelSensitive) {
  135. HalpEnablePCIInterrupt( Vector );
  136. Enabled = TRUE;
  137. }
  138. //
  139. // If the vector is a performance counter vector or one of the
  140. // internal device vectors (serial or keyboard/mouse) then perform
  141. // 21064-specific enable.
  142. //
  143. switch (Vector) {
  144. //
  145. // Performance counter 0 (internal to 21064)
  146. //
  147. case PC0_VECTOR:
  148. case PC0_SECONDARY_VECTOR:
  149. HalpEnable21064PerformanceInterrupt( Vector, Irql );
  150. Enabled = TRUE;
  151. break;
  152. //
  153. // Performance counter 1 (internal to 21064)
  154. //
  155. case PC1_VECTOR:
  156. case PC1_SECONDARY_VECTOR:
  157. HalpEnable21064PerformanceInterrupt( Vector, Irql );
  158. Enabled = TRUE;
  159. break;
  160. } //end switch Vector
  161. //
  162. // Lower IRQL to the previous level.
  163. //
  164. KeLowerIrql(OldIrql);
  165. return Enabled;
  166. }
  167. ULONG
  168. HalpGetSystemInterruptVector(
  169. IN PBUS_HANDLER BusHandler,
  170. IN PBUS_HANDLER RootHandler,
  171. IN ULONG BusInterruptLevel,
  172. IN ULONG BusInterruptVector,
  173. OUT PKIRQL Irql,
  174. OUT PKAFFINITY Affinity
  175. )
  176. /*++
  177. Routine Description:
  178. This function returns the system interrupt vector and IRQL level
  179. corresponding to the specified bus interrupt level and/or vector. The
  180. system interrupt vector and IRQL are suitable for use in a subsequent call
  181. to KeInitializeInterrupt.
  182. We only use InterfaceType, and BusInterruptLevel. BusInterruptVector
  183. for ISA and EISA are the same as the InterruptLevel, so ignore.
  184. Arguments:
  185. BusHandler - Registered BUSHANDLER for the target configuration space
  186. RootHandler - Registered BUSHANDLER for the orginating HalGetBusData
  187. request.
  188. BusInterruptLevel - Supplies the bus specific interrupt level.
  189. BusInterruptVector - Supplies the bus specific interrupt vector.
  190. Irql - Returns the system request priority.
  191. Affinity - Returns the affinity for the requested vector
  192. Return Value:
  193. Returns the system interrupt vector corresponding to the specified device.
  194. --*/
  195. {
  196. INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType;
  197. ULONG BusNumber = BusHandler->BusNumber;
  198. ULONG Vector;
  199. *Affinity = 1;
  200. switch (InterfaceType) {
  201. case ProcessorInternal:
  202. //
  203. // Handle the internal defined for the processor itself
  204. // and used to control the performance counters in the 21064.
  205. //
  206. if( (Vector = HalpGet21064PerformanceVector( BusInterruptLevel,
  207. Irql)) != 0 ){
  208. //
  209. // Performance counter was successfully recognized.
  210. //
  211. return Vector;
  212. } else {
  213. //
  214. // Unrecognized processor interrupt.
  215. //
  216. *Irql = 0;
  217. *Affinity = 0;
  218. return 0;
  219. } //end if Vector
  220. break;
  221. case Isa:
  222. //
  223. // Assumes all ISA devices coming in on same pin
  224. //
  225. *Irql = ISA_DEVICE_LEVEL;
  226. //
  227. // The vector is equal to the specified bus level plus the ISA_VECTOR.
  228. // This is assuming that the ISA levels not assigned Interrupt Levels
  229. // in the Beta programming guide are unused in the LCA system.
  230. // Otherwise, need a different encoding scheme.
  231. //
  232. // Not all interrupt levels are actually supported on Beta;
  233. // Should we make some of them illegal here?
  234. return(BusInterruptLevel + ISA_VECTORS);
  235. break;
  236. case Eisa:
  237. //
  238. // Assumes all EISA devices coming in on same pin
  239. //
  240. *Irql = EISA_DEVICE_LEVEL;
  241. //
  242. // The vector is equal to the specified bus level plus the EISA_VECTOR.
  243. //
  244. return(BusInterruptLevel + EISA_VECTORS);
  245. break;
  246. case PCIBus:
  247. //
  248. // Assumes all PCI devices coming in on same pin
  249. //
  250. *Irql = PCI_DEVICE_LEVEL;
  251. //
  252. // The vector is equal to the specified bus level plus the PCI_VECTOR.
  253. //
  254. return((BusInterruptLevel) + PCI_VECTORS);
  255. break;
  256. default:
  257. //
  258. // Not an interface supported on EB66/Mustang systems
  259. //
  260. *Irql = 0;
  261. *Affinity = 0;
  262. return(0);
  263. break;
  264. } //end switch(InterfaceType)
  265. }
  266. VOID
  267. HalRequestIpi (
  268. IN ULONG Mask
  269. )
  270. /*++
  271. Routine Description:
  272. This routine requests an interprocessor interrupt on a set of processors.
  273. This routine performs no function on an EB66/Mustang because it is a
  274. uni-processor system.
  275. Arguments:
  276. Mask - Supplies the set of processors that are sent an interprocessor
  277. interrupt.
  278. Return Value:
  279. None.
  280. --*/
  281. {
  282. return;
  283. }