// first all the gprs 

    { szGpr0,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR0},
    { szGpr1,     rtCPU | rtRegular | rtExtended | rtInteger | rtFrame, 32, CV_PPC_GPR1},
    { szGpr2,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR2},
    { szGpr3,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR3},
    { szGpr4,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR4},
    { szGpr5,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR5},
    { szGpr6,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR6},
    { szGpr7,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR7},
    { szGpr8,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR8},
    { szGpr9,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR9},
    { szGpr10,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR10},
    { szGpr11,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR11},
    { szGpr12,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR12},
    { szGpr13,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR13},
    { szGpr14,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR14},
    { szGpr15,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR15},
    { szGpr16,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR16},
    { szGpr17,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR17},
    { szGpr18,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR18},
    { szGpr19,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR19},
    { szGpr20,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR20},
    { szGpr21,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR21},
    { szGpr22,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR22},
    { szGpr23,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR23},
    { szGpr24,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR24},
    { szGpr25,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR25},
    { szGpr26,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR26},
    { szGpr27,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR27},
    { szGpr28,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR28},
    { szGpr29,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR29},
    { szGpr30,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR30},
    { szGpr31,    rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR31},

// floating point registers follow 

    { szFpr0,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR0 },
    { szFpr1,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR1 },
    { szFpr2,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR2 },
    { szFpr3,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR3 },
    { szFpr4,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR4 },
    { szFpr5,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR5 },
    { szFpr6,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR6 },
    { szFpr7,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR7 },
    { szFpr8,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR8 },
    { szFpr9,     rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR9 },
    { szFpr10,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR10 },
    { szFpr11,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR11 },
    { szFpr12,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR12 },
    { szFpr13,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR13 },
    { szFpr14,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR14 },
    { szFpr15,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR15 },
    { szFpr16,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR16 },
    { szFpr17,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR17 },
    { szFpr18,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR18 },
    { szFpr19,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR19 },
    { szFpr20,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR20 },
    { szFpr21,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR21 },
    { szFpr22,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR22 },
    { szFpr23,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR23 },
    { szFpr24,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR24 },
    { szFpr25,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR25 },
    { szFpr26,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR26 },
    { szFpr27,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR27 },
    { szFpr28,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR28 },
    { szFpr29,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR29 },
    { szFpr30,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR30 },
    { szFpr31,    rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR31 },

    { szFpscr,   rtFPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_FPSCR },
    { szLr,      rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_LR },
    { szCr,      rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_CR },
    { szCtr,     rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_CTR },
    { szCIA,     rtCPU | rtRegular | rtExtended | rtInteger | rtPC, 32, CV_PPC_PC},
    { szMsr,     rtCPU | rtExtended | rtInteger | rtSpecial  , 32, CV_PPC_MSR},
    { szXer,     rtCPU | rtExtended | rtInteger | rtSpecial  , 32, CV_PPC_XER}