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111 lines
2.6 KiB
111 lines
2.6 KiB
/*
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* |-----------------------------------------------------------|
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* | Copyright (c) 1991 MIPS Computer Systems, Inc. |
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* | All Rights Reserved |
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* |-----------------------------------------------------------|
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* | Restricted Rights Legend |
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* | Use, duplication, or disclosure by the Government is |
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* | subject to restrictions as set forth in |
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* | subparagraph (c)(1)(ii) of the Rights in Technical |
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* | Data and Computer Software Clause of DFARS 52.227-7013. |
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* | MIPS Computer Systems, Inc. |
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* | 950 DeGuigne Drive |
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* | Sunnyvale, CA 94086 |
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* |-----------------------------------------------------------|
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*/
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/* $Header: cosh.s,v 3000.8.1.5 91/08/19 14:55:38 zaineb Exp $ */
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/* Algorithm from Cody and Waite. */
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#include <kxmips.h>
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#include <trans.h>
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#include <fpieee.h>
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#ifdef CRTDLL
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.extern _HUGE_dll
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#define _HUGE _HUGE_dll
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#else
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.extern _HUGE
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#endif
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#define expmax 709.78271289338397
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#define coshmax 710.47586007394386
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.text
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.globl cosh
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.ent cosh
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cosh:
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#define FSIZE 16
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.frame sp, FSIZE, ra
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.mask 0x80000000, -4
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subu sp, FSIZE
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sw ra, FSIZE-4(sp)
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.prologue 1
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li.d $f10, expmax
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abs.d $f12
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c.ole.d $f12, $f10
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bc1f cosh3
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jal exp
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li.d $f10, 0.5
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div.d $f2, $f10, $f0
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mul.d $f0, $f10
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add.d $f0, $f2
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j ret1
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cosh3:
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li.d $f6, coshmax
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li.d $f8, 0.69316101074218750000
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c.ole.d $f12, $f6
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bc1f error
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sub.d $f12, $f8
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jal exp
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li.d $f6, 0.13830277879601902638e-4
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mul.d $f2, $f0, $f6
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add.d $f0, $f2
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j ret1
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error:
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// raise Overflow and return +Infinity
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jal setup_cosh_err
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j ret1
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mfc1 t0, $f13
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sll t0, 1
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srl t0, 20+1
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beq t0, 2047, 1f
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li.d $f0, 0.898846567431158e308
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add.d $f0, $f0
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j ret
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1: mov.d $f0, $f12
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j ret
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ret1: lw ra, FSIZE-4(sp)
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ret: addu sp, FSIZE
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j ra
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.end cosh
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#undef FSIZE
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.extern _except1
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.ent setup_cosh_err
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setup_cosh_err:
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#define FSIZE 48
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.frame sp, FSIZE, ra
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.mask 0x80000000, -4
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subu sp, FSIZE
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sw ra, FSIZE-4(sp)
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.prologue 1
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li $4, (FP_O | FP_P) // exception mask
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li $5, OP_COSH // operation code (funtion name index)
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mfc1.d $6, $f12 // arg1
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l.d $f0, _HUGE // api help says return HUGE_VAL for overflow
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s.d $f0, 16(sp) // default result
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cfc1 t7, $31 // floating point control/status register
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xor t7, t7, 0xf80 // inverse exception enable bits
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sw t7, 24(sp)
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jal _except1
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lw ra, FSIZE-4(sp)
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addu sp, FSIZE
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j ra
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#undef FSIZE
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.end setup_cosh_err
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