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101 lines
4.5 KiB
101 lines
4.5 KiB
/************************************************************************
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* *
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* Copyright 1994 Symbios Logic Inc. All rights reserved. *
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* *
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* This file is confidential and a trade secret of Symbios Logic *
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* The receipt of or possession of this file does not convey any *
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* rights to reproduce or disclose its contents or to manufacture, *
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* use, or sell anything is may describe, in whole, or in part, *
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* without the specific written consent of Symbios Logic Inc *
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* *
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************************************************************************/
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/*+++HDR
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*
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* Version History
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* ---------------
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*
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* Date Who? Description
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* -------- ---- -------------------------------------------------------
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*
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*
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---*/
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#ifndef _SYM53C810_
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#define _SYM53C810_
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//
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// 53C8XX SIOP I/O registers.
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//
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typedef struct _SIOP_REGISTER_BASE {
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UCHAR SCNTL0; // 00 SCSI control 0
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UCHAR SCNTL1; // 01 SCSI control 1
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UCHAR SCNTL2; // 02 SCSI control 2
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UCHAR SCNTL3; // 03 SCSI control 3
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UCHAR SCID; // 04 SCSI chip ID
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UCHAR SXFER; // 05 SCSI transfer
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UCHAR SDID; // 06 SCSI destination ID
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UCHAR GPREG; // 07 general purpose bits
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UCHAR SFBR; // 08 SCSI first byte received
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UCHAR SOCL; // 09 SCSI output control latch
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UCHAR SSID; // 0a SCSI selector id
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UCHAR SBCL; // 0b SCSI bus control lines
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UCHAR DSTAT; // 0c DMA status
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UCHAR SSTAT0; // 0d SCSI status 0
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UCHAR SSTAT1; // 0e SCSI status 1
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UCHAR SSTAT2; // 0f SCSI status 2
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ULONG DSA; // 10-13 data structure address
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UCHAR ISTAT; // 14 interrupt status
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UCHAR RESERVED0[3]; // 15-17 reserved
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UCHAR CTEST0; // 18 chip test 0
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UCHAR CTEST1; // 19 chip test 1
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UCHAR CTEST2; // 1a chip test 2
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UCHAR CTEST3; // 1b chip test 3
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ULONG TEMP; // 1c-1f temporary stack
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UCHAR DFIFO; // 20 DMA fifo
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UCHAR CTEST4; // 21 chip test 4
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UCHAR CTEST5; // 22 chip test 5
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UCHAR CTEST6; // 23 chip test 6
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UCHAR DBC[3]; // 24-26 DMA byte counter
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UCHAR DCMD; // 27 DMA command
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ULONG DNAD; // 28-2b DMA next address for data
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ULONG DSP; // 2c-2f DMA scripts pointer
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UCHAR DSPS[4]; // 30-33 DMA scripts pointer save
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UCHAR SCRATCH[4]; // 34-37 general purpose scratch pad A
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UCHAR DMODE; // 38 DMA mode
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UCHAR DIEN; // 39 DMA interrupt enable
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UCHAR DWT; // 3a DMA watchdog timer
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UCHAR DCNTL; // 3b DMA control
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ULONG ADDER; // 3c-3f sum output of internal adder
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UCHAR SIEN0; // 40 SCSI interrupt enable 0
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UCHAR SIEN1; // 41 SCSI interrupt enable 1
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UCHAR SIST0; // 42 SCSI interrupt status 0
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UCHAR SIST1; // 43 SCSI interrupt status 1
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UCHAR SLPAR; // 44 SCSI longitudinal parity
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UCHAR SWIDE; // 45 SCSI wide residue
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UCHAR MACNTL; // 46 memory access control
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UCHAR GPCNTL; // 47 general purpose control
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UCHAR STIME0; // 48 SCSI timer 0
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UCHAR STIME1; // 49 SCSI timer 1
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UCHAR RESPID0; // 4a response ID low-byte
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UCHAR RESPID1; // 4b response ID high-byte
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UCHAR STEST0; // 4c SCSI test 0
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UCHAR STEST1; // 4d SCSI test 1
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UCHAR STEST2; // 4e SCSI test 2
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UCHAR STEST3; // 4f SCSI test 3
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UCHAR SIDL; // 50-51 SCSI input data latch
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UCHAR SIDL_LOWER;
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UCHAR RESERVED3[2]; // 52-53 reserved
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UCHAR SODL; // 54-55 SCSI output data latch
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UCHAR SODL_LOWER;
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UCHAR RESERVED4[2]; // 56-57 reserved
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UCHAR SBDL; // 58-59 SCSI bus data lines
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UCHAR SBDL_LOWER;
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UCHAR RESERVED5[2]; // 5a-5b reserved
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ULONG SCRATCHB; // 5c-5f general purpose scratch pad B
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} SIOP_REGISTER_BASE, *PSIOP_REGISTER_BASE;
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#endif
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