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526 lines
10 KiB
526 lines
10 KiB
page
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;***********************************************************************
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;
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; (C) Copyright 1992 Trantor Systems, Ltd.
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; All Rights Reserved.
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;
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; This program is an unpublished copyrighted work which is proprietary
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; to Trantor Systems, Ltd. and contains confidential information that
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; is not to be reproduced or disclosed to any other person or entity
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; without prior written consent from Trantor Systems, Ltd. in each
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; and every instance.
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;
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; WARNING: Unauthorized reproduction of this program as well as
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; unauthorized preparation of derivative works based upon the
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; program or distribution of copies by sale, rental, lease or
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; lending are violations of federal copyright laws and state trade
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; secret laws, punishable by civil and criminal penalties.
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;
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;***********************************************************************
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title EP3C2.ASM
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;-----------------------------------------------------------------------
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;
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; EP3C2.ASM
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;
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; FIFO I/O Routines for the EP3C chip.
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; Assembly coded for speed. These are only some of the routines
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; needed for the EP3C. The rest are in EP3C.C.
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;
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; History
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; -------
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; 05-17-93 JAP First, from ep3c.c
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;
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;-----------------------------------------------------------------------
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;-----------------------------------------------------------------------
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; stack frame equates
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;-----------------------------------------------------------------------
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ep3c_param2 equ 12
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ep3c_param1 equ 8
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ep3c_retAdrs equ 4
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ep3c_bp equ 0
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ep3c_pbytes equ ep3c_param2
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ep3c_baseIoAddress equ ep3c_param1
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;-----------------------------------------------------------------------
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; Macros
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;-----------------------------------------------------------------------
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;-----------------------------------------------------------------------
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; get_params
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;
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; Puts parameters into registers:
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; edx -> baseIoAddress
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; ds:[edi] -> pbytes
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;-----------------------------------------------------------------------
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get_params macro
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ifdef MODE_32BIT
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mov edi, dword ptr [ebp].ep3c_pbytes
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mov edx, dword ptr [ebp].ep3c_baseIoAddress
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else
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mov edi, word ptr ss:[bp].ep3c_pbytes
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mov ds, word ptr ss:[bp].ep3c_pbytes+2
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mov edx, word ptr ss:[bp].ep3c_baseIoAddress
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endif ;MODE_32BIT
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endm
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;-----------------------------------------------------------------------
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; Routines
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;-----------------------------------------------------------------------
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;-----------------------------------------------------------------------
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; EP3CReadFifoUniDir
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;
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; VOID EP3CReadFifoUniDir (PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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;
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; Reads bytes for uni-directional parallel port from the 53c400
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; 128 byte buffer. The register must already be set the the
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; 53c400 buffer register.
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;
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;-----------------------------------------------------------------------
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EP3CReadFifoUniDir proc far
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push ds
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push edi
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get_params
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mov ecx, 128
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loop0:
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mov al, 0x80
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out dx, al ;select high nibble
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jmp delay0
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delay0:
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add edx,2 ;DX -> ctl reg
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mov al,P_AFX ;assert bufen and afx
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out dx,al ;assert dreg read
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jmp delay1
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delay1:
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dec edx ;DX -> stat reg
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in al,dx ;read high nibble
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jmp delay2
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delay2:
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mov ah,al
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shl ah,1
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and ah,0f0h ;AH -> adj high nibble
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dec edx ;DX -> data reg
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sub al,al
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out dx,al ;select low nibble
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jmp delay3
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delay3:
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inc edx ;DX -> stat reg
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in al,dx ;read low nibble
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shr al,1
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shr al,1
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shr al,1
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and al,0fh ;AL = adj low nibble
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or al,ah ;AL = recombined byte
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mov [edi],al ;store
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inc edi ;bump buf ptr
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inc edx ;DX -> ctl reg
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xor al,al ;negate afx (bufen stays asserted)
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out dx,al ;end read
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jmp delay4
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delay4:
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sub edx,2 ;DX -> data reg
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dec ecx
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jnz loop0
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pop edi
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pop ds
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ret
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EP3CReadFifoUniDir endp
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;-----------------------------------------------------------------------
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;
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; EP3CReadFifoUniDirSlow
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;
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; VOID EP3CReadFifoUniDirSlow (PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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;
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; Reads bytes for uni-directional parallel port from the 53c400
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; 128 byte buffer. The register must already be set the the
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; 53c400 buffer register.
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;
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; USES FULL HANDSHAKING
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;
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;-----------------------------------------------------------------------
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EP3CReadFifoUniDirSlow proc far
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push ds
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push edi
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get_params
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inc edx // edx - status register
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mov ecx, 128
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loop0:
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dec edx // edx - data register
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mov al, 0x80
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out dx,al // select high nibble
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jmp delay0
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delay0:
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add edx, 2 // DX -> ctl reg
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mov al, P_AFX // assert bufen and afx
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out dx, al // assert dreg read
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; wait till ready, P_BUSY asserted
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dec edx // edx - status register
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loop1:
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in al,dx
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test al, P_BUSY
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jnz loop1
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; delay to make sure we get high nibble in
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jmp delay01
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delay01:
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in al,dx
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mov ah,al
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shl ah,1
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and ah,0f0h // AH -> adj high nibble
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dec edx // DX -> data reg
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sub al,al
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out dx,al // select low nibble
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jmp delay3
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delay3:
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inc edx // DX -> stat reg
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in al,dx // read low nibble
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shr al,1
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shr al,1
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shr al,1
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and al,0fh // AL = adj low nibble
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or al,ah // AL = recombined byte
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mov [edi],al // store
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inc edi // bump buf ptr
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inc edx // DX -> ctl reg
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xor al,al // negate afx (bufen stays asserted)
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out dx,al // end read
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dec edx // DX -> status register
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; wait for P_BUSY deasserted
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loop2:
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in al,dx
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test al, P_BUSY
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jz loop2
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dec ecx
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jnz loop0
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pop edi
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pop ds
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ret
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EP3CReadFifoUniDirSlow endp
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//----------------------------------------------------------------------
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//
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// VOID EP3CReadFifoBiDir
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//
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// Reads bytes for bi-directional parallel port from the 53c400
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// 128 byte buffer. The register must already be set the the
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// 53c400 buffer register.
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//
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//----------------------------------------------------------------------
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VOID EP3CReadFifoBiDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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{
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_asm {
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push ds
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push edi
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#ifdef MODE_32BIT
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mov edi,pbytes
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mov edx, baseIoAddress
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#else
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mov edi, word ptr pbytes
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mov ds, word ptr pbytes+2
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mov edx, word ptr baseIoAddress
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#endif // MODE_32BIT
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mov ecx, 128
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add edx, 2 // edx - control register
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loop0:
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mov al, P_BUFEN + P_AFX
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out dx, al
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jmp delay0
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delay0:
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sub edx,2 // edx - data register
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in al,dx
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mov [edi], al
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inc edi
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add edx,2 // edx - control register
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mov al, P_BUFEN
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out dx, al
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jmp delay1 // is this needed, there is a loop?
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delay1:
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dec ecx
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jnz loop0
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xor al,al // leave control regiser 0'd
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out dx, al
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pop edi
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pop ds
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}
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}
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//----------------------------------------------------------------------
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//
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// VOID EP3CReadFifoBiDirSlow
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//
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// Reads bytes for bi-directional parallel port from the 53c400
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// 128 byte buffer. The register must already be set the the
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// 53c400 buffer register.
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//
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// USES FULL HANDSHAKING
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//
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//----------------------------------------------------------------------
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VOID EP3CReadFifoBiDirSlow(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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{
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_asm {
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push ds
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push edi
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#ifdef MODE_32BIT
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mov edi,pbytes
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mov edx, baseIoAddress
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#else
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mov edi, word ptr pbytes
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mov ds, word ptr pbytes+2
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mov edx, word ptr baseIoAddress
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#endif // MODE_32BIT
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mov ecx, 128
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add edx, 0x02 // edx - control register
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// wait for data to be ready, P_BUSY asserted
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loop0:
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mov al, P_BUFEN + P_AFX
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out dx, al
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dec edx // edx - status register
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loop1:
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in al,dx
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test al, P_BUSY
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jnz loop1
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dec edx // edx - data register
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in al,dx
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mov [edi], al
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inc edi
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add edx,2 // edx - control register
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// end data read cycle
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mov al, P_BUFEN
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out dx, al
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dec edx // edx - status register
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// wait for P_BUSY deasserted
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loop2:
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in al,dx
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test al, P_BUSY
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jz loop2
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inc edx // edx - control register
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dec ecx
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jnz loop0
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xor al,al // leave control regiser 0'd
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out dx, al
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pop edi
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pop ds
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}
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}
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//----------------------------------------------------------------------
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//
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// VOID EP3CWriteFifoUniDir
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//
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// Writes bytes thru uni-directional parallel port to the 53c400
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// 128 byte buffer. The register must already be set the the
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// 53c400 buffer register.
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//
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//----------------------------------------------------------------------
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VOID EP3CWriteFifoUniDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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{
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_asm {
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push ds
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push edi
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#ifdef MODE_32BIT
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mov edi,pbytes
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mov edx, baseIoAddress
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#else
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mov edi, word ptr pbytes
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mov ds, word ptr pbytes+2
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mov edx, word ptr baseIoAddress
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#endif // MODE_32BIT
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mov ecx, 128
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loop0:
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mov al,[edi]
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out dx,al
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inc edi
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add edx,2 ;DX -> ctl reg
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mov al,P_STB ;assert bufen, stb
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out dx,al
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or al,P_AFX ;assert dreg write
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out dx,al
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jmp delay0
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delay0:
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;leave bufen asserted
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mov al,0 ; and negate afx, stb
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out dx,al ;end write
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jmp delay1
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delay1:
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sub edx,2 ;DX -> data reg
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dec ecx
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jnz loop0
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// let's leave control register 0'd for all these fifo routines...
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// add edx,2 ;DX -> ctl reg
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// or al,P_BUFEN ;negate bufen
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// out dx,al
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jmp delay2
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delay2:
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pop edi
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pop ds
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}
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}
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//----------------------------------------------------------------------
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//
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// VOID EP3CWriteFifoUniDirSlow
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//
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// Writes bytes thru uni-directional parallel port to the 53c400
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// 128 byte buffer. The register must already be set the the
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// 53c400 buffer register.
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//
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// USES FULL HANDSHAKING
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//
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//----------------------------------------------------------------------
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VOID EP3CWriteFifoUniDirSlow(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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{
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_asm {
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push ds
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push edi
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#ifdef MODE_32BIT
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mov edi,pbytes
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mov edx, baseIoAddress
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#else
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mov edi, word ptr pbytes
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mov ds, word ptr pbytes+2
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mov edx, word ptr baseIoAddress
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#endif // MODE_32BIT
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mov ecx, 128
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loop0:
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mov al,[edi]
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out dx,al
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inc edi
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add edx,2 ;DX -> ctl reg
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mov al,P_STB ;assert bufen, stb
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out dx,al
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or al,P_AFX ;assert dreg write
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out dx,al
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// wait till ready, P_BUSY asserted
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dec edx // edx - status register
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loop1:
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in al,dx
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test al, P_BUSY
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jnz loop1
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inc edx // edx - control register
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;leave bufen asserted
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mov al,0 ; and negate afx, stb
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out dx,al ;end write
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dec edx // edx - status register
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// wait for P_BUSY deasserted
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loop2:
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in al,dx
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test al, P_BUSY
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jz loop2
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dec edx // edx - data register
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dec ecx
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jnz loop0
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// let's leave control register 0'd for all these fifo routines...
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// add edx,2 ;DX -> ctl reg
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// or al,P_BUFEN ;negate bufen
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// out dx,al
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pop edi
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pop ds
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}
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}
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