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581 lines
11 KiB
581 lines
11 KiB
/*++
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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olisproc.c
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Abstract:
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SystemPro Start Next Processor c code.
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This module implements the initialization of the system dependent
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functions that define the Hardware Architecture Layer (HAL) for an
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MP Compaq SystemPro
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Author:
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Ken Reneris (kenr) 22-Jan-1991
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Environment:
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Kernel mode only.
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Revision History:
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Bruno Sartirana (o-obruno) 3-Mar-92
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Added support for the Olivetti LSX5030.
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--*/
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#include "halp.h"
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UCHAR HalName[] = "Olivetti LSX5030 MP Hal";
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VOID
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HalpMapCR3 (
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IN ULONG VirtAddress,
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IN PVOID PhysicalAddress,
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IN ULONG Length
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);
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ULONG
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HalpBuildTiledCR3 (
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IN PKPROCESSOR_STATE ProcessorState
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);
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VOID
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HalpFreeTiledCR3 (
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VOID
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);
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//LSX5030 start
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ULONG
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HalpGetIpiIrqNumber();
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VOID
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HalpIpiHandler(
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VOID
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);
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ULONG
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HalpGetNumberOfProcessors();
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#ifdef HALOLI_DBG
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VOID
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DbgDisplay(
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IN UCHAR Code
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);
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# define DBG_DISPLAY(x) DbgDisplay(x)
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#else
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# define DBG_DISPLAY(x)
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#endif
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/***
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* Olivetti LSX5030 varialbles and constants
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*/
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ULONG IpiVector; // Inter-processor interrupt vector
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ULONG IdtIpiVector; // Inter-processor interrupt vector # in
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// the IDT
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ULONG HalpCpuCount; // total number of CPU's available
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ULONG CpuLeft; // number of CPU's not started yet
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ULONG NextCpuToStart = 1; // next CPU logical # to start
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// LSX5030 end
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#define LOW_MEMORY 0x000100000
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#define MAX_PT 8
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extern VOID __cdecl StartPx_PMStub(VOID);
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PUCHAR MpLowStub; // pointer to low memory bootup stub
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PVOID MpLowStubPhysicalAddress; // pointer to low memory bootup stub
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PUCHAR MppIDT; // pointer to physical memory 0:0
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PVOID MpFreeCR3[MAX_PT]; // remember pool memory to free
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BOOLEAN
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HalpInitMP (
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IN ULONG Phase,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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Allows MP initialization from HalInitSystem.
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Arguments:
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Same as HalInitSystem
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Return Value:
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none.
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--*/
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{
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PKPCR pPCR;
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KIRQL CurrentIrql;
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pPCR = KeGetPcr();
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if (Phase == 0) {
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//
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// Only Processor 0 runs the phase 0 initializtion code
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//
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//DBG_DISPLAY(0x00);
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MppIDT = HalpMapPhysicalMemory (0, 1);
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//LSX5030 start
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IpiVector = HalpGetIpiIrqNumber();
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IdtIpiVector = IpiVector + PRIMARY_VECTOR_BASE;
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HalpCpuCount = HalpGetNumberOfProcessors();
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CpuLeft = HalpCpuCount - 1;
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if (CpuLeft == 0) {
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//
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// Only 1 CPU available
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//
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return TRUE;
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}
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//
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// Register IPI handler
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//
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KiSetHandlerAddressToIDT(PRIMARY_VECTOR_BASE + IpiVector,
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HalpIpiHandler);
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//
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// Enable inter-processor interrupts on CPU 0
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//
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HalEnableSystemInterrupt(PRIMARY_VECTOR_BASE + IpiVector,
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IPI_LEVEL, 0);
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//LSX5030 end
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//
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// Allocate some low memory for processor bootup stub
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//
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MpLowStubPhysicalAddress = (PVOID)HalpAllocPhysicalMemory (LoaderBlock,
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LOW_MEMORY, 1, FALSE);
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if (!MpLowStubPhysicalAddress)
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return TRUE;
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MpLowStub = (PCHAR) HalpMapPhysicalMemory (MpLowStubPhysicalAddress, 1);
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} else {
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//
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// Phase 1
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//
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//DBG_DISPLAY(0x10);
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//
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// Check to see if this is not processor 0
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//
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if (pPCR->Prcb->Number != 0) {
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//DBG_DISPLAY(0x11);
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//
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// It is not processor 0. Mask the PICs and start the clock.
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//
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//
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// Mask the PICs to reflect the current Irql
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//
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CurrentIrql = KeGetCurrentIrql();
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CurrentIrql = KfRaiseIrql (CurrentIrql);
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//
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// Initialize the timer 1 counter 0
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//
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HalpInitializeClock();
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//DBG_DISPLAY(0x12);
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//
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// Initialize the clock interrupt vector and enable the
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// clock interrupt.
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//
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KiSetHandlerAddressToIDT(CLOCK_VECTOR, HalpClockInterrupt );
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HalEnableSystemInterrupt(CLOCK_VECTOR, CLOCK2_LEVEL, Latched);
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//DBG_DISPLAY(0x13);
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}
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}
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return TRUE;
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}
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VOID
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HalReportResourceUsage (
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VOID
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)
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/*++
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Routine Description:
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The registery is now enabled - time to report resources which are
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used by the HAL.
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Arguments:
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Return Value:
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--*/
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{
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ANSI_STRING AHalName;
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UNICODE_STRING UHalName;
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HalInitSystemPhase2 ();
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RtlInitAnsiString (&AHalName, HalName);
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RtlAnsiStringToUnicodeString (&UHalName, &AHalName, TRUE);
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HalpReportResourceUsage (
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&UHalName, // descriptive name
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Eisa // The LSX5030 is an Eisa machine
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);
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RtlFreeUnicodeString (&UHalName);
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}
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BOOLEAN
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HalAllProcessorsStarted (
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VOID
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)
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{
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return TRUE;
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}
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VOID
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HalpResetAllProcessors (
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VOID
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)
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{
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// Just return, that will invoke the standard PC reboot code
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}
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ULONG
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HalpBuildTiledCR3 (
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IN PKPROCESSOR_STATE ProcessorState
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)
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/*++
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Routine Description:
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When the x86 processor is reset it starts in real-mode. In order to
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move the processor from real-mode to protected mode with flat addressing
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the segment which loads CR0 needs to have it's linear address mapped
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to machine the phyiscal location of the segment for said instruction so
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the processor can continue to execute the following instruction.
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This function is called to built such a tiled page directory. In
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addition, other flat addresses are tiled to match the current running
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flat address for the new state. Once the processor is in flat mode,
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we move to a NT tiled page which can then load up the remaining processors
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state.
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Arguments:
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ProcessorState - The state the new processor should start in.
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Return Value:
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Physical address of Tiled page directory
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--*/
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{
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#define GetPdeAddress(va) ((PHARDWARE_PTE)((((((ULONG)(va)) >> 22) & 0x3ff) << 2) + (PUCHAR)MpFreeCR3[0]))
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#define GetPteAddress(va) ((PHARDWARE_PTE)((((((ULONG)(va)) >> 12) & 0x3ff) << 2) + (PUCHAR)pPageTable))
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// bugbug kenr 27mar92 - fix physical memory usage!
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MpFreeCR3[0] = ExAllocatePool (NonPagedPool, PAGE_SIZE);
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RtlZeroMemory (MpFreeCR3[0], PAGE_SIZE);
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//
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// Map page for real mode stub (one page)
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//
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HalpMapCR3 ((ULONG) MpLowStubPhysicalAddress,
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MpLowStubPhysicalAddress,
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PAGE_SIZE);
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//
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// Map page for protect mode stub (one page)
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//
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HalpMapCR3 ((ULONG) &StartPx_PMStub, NULL, 0x1000);
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//
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// Map page(s) for processors GDT
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//
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HalpMapCR3 (ProcessorState->SpecialRegisters.Gdtr.Base, NULL,
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ProcessorState->SpecialRegisters.Gdtr.Limit);
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//
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// Map page(s) for processors IDT
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//
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HalpMapCR3 (ProcessorState->SpecialRegisters.Idtr.Base, NULL,
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ProcessorState->SpecialRegisters.Idtr.Limit);
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return MmGetPhysicalAddress (MpFreeCR3[0]).LowPart;
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}
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VOID
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HalpMapCR3 (
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IN ULONG VirtAddress,
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IN PVOID PhysicalAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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Called to build a page table entry for the passed page directory.
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Used to build a tiled page directory with real-mode & flat mode.
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Arguments:
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VirtAddress - Current virtual address
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PhysicalAddress - Optional. Physical address to be mapped to, if passed
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as a NULL then the physical address of the passed
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virtual address is assumed.
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Length - number of bytes to map
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Return Value:
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none.
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--*/
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{
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ULONG i;
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PHARDWARE_PTE PTE;
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PVOID pPageTable;
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PHYSICAL_ADDRESS pPhysicalPage;
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while (Length) {
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PTE = GetPdeAddress (VirtAddress);
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if (!PTE->PageFrameNumber) {
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pPageTable = ExAllocatePool (NonPagedPool, PAGE_SIZE);
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RtlZeroMemory (pPageTable, PAGE_SIZE);
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for (i=0; i<MAX_PT; i++) {
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if (!MpFreeCR3[i]) {
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MpFreeCR3[i] = pPageTable;
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break;
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}
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}
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ASSERT (i<MAX_PT);
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pPhysicalPage = MmGetPhysicalAddress (pPageTable);
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PTE->PageFrameNumber = (pPhysicalPage.LowPart >> PAGE_SHIFT);
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PTE->Valid = 1;
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PTE->Write = 1;
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}
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pPhysicalPage.LowPart = PTE->PageFrameNumber << PAGE_SHIFT;
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pPhysicalPage.HighPart = 0;
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pPageTable = MmMapIoSpace (pPhysicalPage, PAGE_SIZE, TRUE);
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PTE = GetPteAddress (VirtAddress);
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if (!PhysicalAddress) {
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PhysicalAddress = (PVOID)MmGetPhysicalAddress ((PVOID)VirtAddress).LowPart;
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}
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PTE->PageFrameNumber = ((ULONG) PhysicalAddress >> PAGE_SHIFT);
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PTE->Valid = 1;
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PTE->Write = 1;
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MmUnmapIoSpace (pPageTable, PAGE_SIZE);
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PhysicalAddress = 0;
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VirtAddress += PAGE_SIZE;
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if (Length > PAGE_SIZE) {
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Length -= PAGE_SIZE;
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} else {
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Length = 0;
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}
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}
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}
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VOID
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HalpFreeTiledCR3 (
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VOID
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)
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/*++
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Routine Description:
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Free's any memory allocated when the tiled page directory was built.
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Arguments:
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none
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Return Value:
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none
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--*/
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{
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ULONG i;
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for (i=0; MpFreeCR3[i]; i++) {
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ExFreePool (MpFreeCR3[i]);
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MpFreeCR3[i] = 0;
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}
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}
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VOID
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HalpInitializeProcessor (
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IN UCHAR ProcessorNumber
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)
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/*++
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Routine Description:
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This function initializes the current CPU's PIC's and clock.
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Arguments:
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ProcessorNumber: current processor
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Return Value:
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None.
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--*/
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{
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KIRQL CurrentIrql;
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//DBG_DISPLAY(0x70);
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// if (ProcessorNumber != '\0') {
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//
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// For processor 0 only initialize PICs and stall execution counter.
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//
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HalpInitializePICs();
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//
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// Now that the PICs are initialized, we need to mask them to
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// reflect the current Irql
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//
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//DBG_DISPLAY(0x71);
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CurrentIrql = KeGetCurrentIrql();
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//DBG_DISPLAY(0x72);
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KeRaiseIrql(CurrentIrql, &CurrentIrql);
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//DBG_DISPLAY(0x73);
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//
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// Note that HalpInitializeClock MUST be called after
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// HalpInitializeStallExecution, because
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// HalpInitializeStallExecution reprograms the timer.
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//
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HalpInitializeStallExecution(ProcessorNumber);
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//DBG_DISPLAY(0x74);
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// }
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//
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// Register IPI handler
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//
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KiSetHandlerAddressToIDT(PRIMARY_VECTOR_BASE + IpiVector , HalpIpiHandler);
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//DBG_DISPLAY(0x75);
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//
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// Enable inter-processor interrupts on this CPU
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//
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HalEnableSystemInterrupt(PRIMARY_VECTOR_BASE + IpiVector,
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(KIRQL) IPI_LEVEL,
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(KINTERRUPT_MODE) 0);
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//DBG_DISPLAY(0x76);
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return;
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}
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VOID
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HalpInitOtherBuses (
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VOID
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)
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{
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}
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NTSTATUS
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HalpGetMcaLog (
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OUT PMCA_EXCEPTION Exception,
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OUT PULONG ReturnedLength
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)
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{
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return STATUS_NOT_SUPPORTED;
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}
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NTSTATUS
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HalpMcaRegisterDriver(
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IN PMCA_DRIVER_INFO DriverInfo
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)
|
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{
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return STATUS_NOT_SUPPORTED;
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}
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ULONG
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FASTCALL
|
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HalSystemVectorDispatchEntry (
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IN ULONG Vector,
|
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OUT PKINTERRUPT_ROUTINE **FlatDispatch,
|
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OUT PKINTERRUPT_ROUTINE *NoConnection
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)
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{
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return FALSE;
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}
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