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703 lines
16 KiB
703 lines
16 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1992, 1993, 1994 Digital Equipment Corporation
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Module Name:
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pciir.c
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Abstract:
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The module provides the interrupt support for the Mikasa's PCI
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interrupts.
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Author:
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James Livingston 2-May-1994
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Revision History:
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Janet Schneider (Digital) 27-July-1995
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Added support for the Noritake.
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--*/
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#include "halp.h"
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//
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// Define external function prototypes
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//
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UCHAR
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HalpAcknowledgeMikasaPciInterrupt(
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PVOID ServiceContext
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);
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UCHAR
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HalpAcknowledgeNoritakePciInterrupt(
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PVOID ServiceContext
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);
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UCHAR
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HalpAcknowledgeCorellePciInterrupt(
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PVOID ServiceContext
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);
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//
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// Import save area for PCI interrupt mask register.
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//
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USHORT HalpMikasaPciInterruptMask;
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USHORT HalpNoritakePciInterrupt1Mask;
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USHORT HalpNoritakePciInterrupt2Mask;
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USHORT HalpNoritakePciInterrupt3Mask;
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USHORT HalpCorellePciInterrupt1Mask;
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USHORT HalpCorellePciInterrupt2Mask;
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//
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// Reference for globals defined in I/O mapping module.
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//
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extern PVOID HalpMikasaPciIrQva;
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extern PVOID HalpMikasaPciImrQva;
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extern PVOID HalpNoritakePciIr1Qva;
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extern PVOID HalpNoritakePciIr2Qva;
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extern PVOID HalpNoritakePciIr3Qva;
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extern PVOID HalpNoritakePciImr1Qva;
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extern PVOID HalpNoritakePciImr2Qva;
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extern PVOID HalpNoritakePciImr3Qva;
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extern PVOID HalpCorellePciIr1Qva;
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extern PVOID HalpCorellePciIr2Qva;
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extern PVOID HalpCorellePciImr1Qva;
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extern PVOID HalpCorellePciImr2Qva;
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//
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// Define reference to platform identifier
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//
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extern BOOLEAN HalpNoritakePlatform;
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extern BOOLEAN HalpCorellePlatform;
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VOID
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HalpInitializeMikasaPciInterrupts(
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the Mikasa PCI interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Initialize the Mikasa PCI interrupts. There is a single interrupt mask
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// that permits individual interrupts to be enabled or disabled by
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// setting the appropriate bit in the interrupt mask register. We
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// initialize them all to "disabled".
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//
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HalpMikasaPciInterruptMask = 0;
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WRITE_PORT_USHORT( (PUSHORT)HalpMikasaPciImrQva,
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HalpMikasaPciInterruptMask );
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}
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VOID
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HalpInitializeNoritakePciInterrupts(
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the Noritake PCI interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Initialize the Noritake PCI interrupts. There are three interrupt masks
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// that permit individual interrupts to be enabled or disabled by
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// setting the appropriate bit in the interrupt mask register. We
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// initialize them all to "disabled", except for the SUM bits. (Bit 0
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// in IR1, and bits 0 and 1 in IR2.)
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//
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HalpNoritakePciInterrupt1Mask = 0x1;
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr1Qva,
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HalpNoritakePciInterrupt1Mask );
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HalpNoritakePciInterrupt2Mask = 0x3;
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr2Qva,
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HalpNoritakePciInterrupt2Mask );
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HalpNoritakePciInterrupt3Mask = 0x0;
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr3Qva,
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HalpNoritakePciInterrupt3Mask );
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}
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VOID
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HalpInitializeCorellePciInterrupts(
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the Corelle PCI interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Initialize the Corelle PCI interrupts. There are 2 interrupt masks
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// that permits individual interrupts to be enabled or disabled by
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// setting the appropriate bit in the interrupt mask register. We will
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// initialize them all to "disabled" except bit 0 of interrupt register 1
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// which is the sum of all interrupts in interrupt register 2.
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//
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HalpCorellePciInterrupt1Mask = 0x1;
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WRITE_PORT_USHORT( (PUSHORT)HalpCorellePciImr1Qva,
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HalpCorellePciInterrupt1Mask );
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HalpCorellePciInterrupt2Mask = 0x0;
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WRITE_PORT_USHORT( (PUSHORT)HalpCorellePciImr2Qva,
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HalpCorellePciInterrupt2Mask );
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}
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VOID
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HalpDisableMikasaPciInterrupt(
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IN ULONG Vector
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)
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/*++
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Routine Description:
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This function disables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is disabled.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0, offset by one.
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//
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Vector -= PCI_VECTORS + 1;
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//
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// Get the current state of the interrupt mask register, then set
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// the bit corresponding to the adjusted value of Vector to zero,
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// to disable that PCI interrupt.
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//
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HalpMikasaPciInterruptMask =
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READ_PORT_USHORT( (PUSHORT)HalpMikasaPciImrQva );
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HalpMikasaPciInterruptMask &= (USHORT) ~(1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpMikasaPciImrQva,
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HalpMikasaPciInterruptMask );
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}
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VOID
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HalpDisableNoritakePciInterrupt(
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IN ULONG Vector
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)
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/*++
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Routine Description:
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This function disables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is disabled.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0.
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//
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Vector -= PCI_VECTORS;
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//
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// First we must determine which interrupt register the interrupt is in.
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// In each case, subtract the register offset to get the bit position in
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// the interrupt register. Then, get the current state of the interrupt
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// mask register. Finally, set the bit corresponding to the adjusted value
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// of Vector to zero, to disable that PCI interrupt.
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//
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if( Vector >= REGISTER_2_VECTOR_OFFSET ) {
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if( Vector >= REGISTER_3_VECTOR_OFFSET ) {
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//
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// The interrupt is in Interrupt Register 3.
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//
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Vector -= REGISTER_3_VECTOR_OFFSET;
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HalpNoritakePciInterrupt3Mask = READ_PORT_USHORT(
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(PUSHORT)HalpNoritakePciImr3Qva );
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HalpNoritakePciInterrupt3Mask &= (USHORT) ~(1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr3Qva,
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HalpNoritakePciInterrupt3Mask );
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} else {
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//
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// The interrupt is in Interrupt Register 2.
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//
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Vector -= REGISTER_2_VECTOR_OFFSET;
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HalpNoritakePciInterrupt2Mask = READ_PORT_USHORT(
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(PUSHORT)HalpNoritakePciImr2Qva );
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HalpNoritakePciInterrupt2Mask &= (USHORT) ~(1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr2Qva,
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HalpNoritakePciInterrupt2Mask );
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}
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} else {
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//
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// The interrupt is in Interrupt Register 1.
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//
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Vector -= REGISTER_1_VECTOR_OFFSET;
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HalpNoritakePciInterrupt1Mask =
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READ_PORT_USHORT( (PUSHORT)HalpNoritakePciImr1Qva );
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HalpNoritakePciInterrupt1Mask &= (USHORT) ~(1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr1Qva,
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HalpNoritakePciInterrupt1Mask );
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}
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}
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VOID
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HalpDisableCorellePciInterrupt(
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IN ULONG Vector
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)
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/*++
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Routine Description:
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This function disables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is disabled.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0.
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//
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Vector -= PCI_VECTORS;
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//
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// First we must determine which interrupt register the interrupt is in.
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// Then, get the current state of the interrupt mask register. Finally,
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// set the bit corresponding to the adjusted value of Vector to zero, to
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// disable that PCI interrupt.
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//
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if ( Vector >= CORELLE_INTERRUPT2_OFFSET ) {
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//
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// The interrupt is in interrupt register 2
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//
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Vector -= CORELLE_INTERRUPT2_OFFSET;
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HalpCorellePciInterrupt2Mask =
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READ_PORT_USHORT((PUSHORT)HalpCorellePciImr2Qva );
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HalpCorellePciInterrupt2Mask &= (USHORT) ~(1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpCorellePciImr2Qva,
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HalpCorellePciInterrupt2Mask );
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} else {
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//
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// The interrupt is in interrupt register 1
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//
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Vector -= CORELLE_INTERRUPT1_OFFSET;
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HalpCorellePciInterrupt1Mask =
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READ_PORT_USHORT( (PUSHORT)HalpCorellePciImr1Qva );
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HalpCorellePciInterrupt1Mask &= (USHORT) ~(1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpCorellePciImr1Qva,
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HalpCorellePciInterrupt1Mask );
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}
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}
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VOID
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HalpEnableMikasaPciInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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)
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/*++
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Routine Description:
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This function enables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is enabled.
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
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Latched (ignored for Mikasa PCI interrupts; they're always levels).
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0, offset by one.
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//
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Vector -= PCI_VECTORS + 1;
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//
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// Get the current state of the interrupt mask register, then set
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// the bit corresponding to the adjusted value of Vector to one,
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// to enable that PCI interrupt.
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//
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HalpMikasaPciInterruptMask =
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READ_PORT_USHORT( (PUSHORT)HalpMikasaPciImrQva );
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HalpMikasaPciInterruptMask |= (USHORT) (1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpMikasaPciImrQva,
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HalpMikasaPciInterruptMask );
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}
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VOID
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HalpEnableNoritakePciInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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)
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/*++
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Routine Description:
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This function enables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is enabled.
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
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Latched (ignored for Mikasa PCI interrupts; they're always levels).
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0.
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//
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Vector -= PCI_VECTORS;
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//
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// First we must determine which interrupt register the interrupt is in.
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// In each case, subtract the register offset to get the bit position in
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// the interrupt register. Then, get the current state of the interrupt
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// mask register. Finally, set the bit corresponding to the adjusted value
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// of Vector to one, to enable that PCI interrupt.
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//
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if( Vector >= REGISTER_2_VECTOR_OFFSET ) {
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if( Vector >= REGISTER_3_VECTOR_OFFSET ) {
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//
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// The interrupt is in Interrupt Register 3.
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//
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Vector -= REGISTER_3_VECTOR_OFFSET;
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HalpNoritakePciInterrupt3Mask = READ_PORT_USHORT(
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(PUSHORT)HalpNoritakePciImr3Qva );
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HalpNoritakePciInterrupt3Mask |= (USHORT) (1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr3Qva,
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HalpNoritakePciInterrupt3Mask );
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} else {
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//
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// The interrupt is in Interrupt Register 2.
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//
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Vector -= REGISTER_2_VECTOR_OFFSET;
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HalpNoritakePciInterrupt2Mask = READ_PORT_USHORT(
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(PUSHORT)HalpNoritakePciImr2Qva );
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HalpNoritakePciInterrupt2Mask |= (USHORT) (1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr2Qva,
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HalpNoritakePciInterrupt2Mask );
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}
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} else {
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//
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// The interrupt is in Interrupt Register 1.
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//
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Vector -= REGISTER_1_VECTOR_OFFSET;
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HalpNoritakePciInterrupt1Mask =
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READ_PORT_USHORT( (PUSHORT)HalpNoritakePciImr1Qva );
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HalpNoritakePciInterrupt1Mask |= (USHORT) (1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpNoritakePciImr1Qva,
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HalpNoritakePciInterrupt1Mask );
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}
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}
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VOID
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HalpEnableCorellePciInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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)
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/*++
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Routine Description:
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This function enables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is enabled.
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
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Latched (ignored for Mikasa PCI interrupts; they're always levels).
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0.
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//
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Vector -= PCI_VECTORS;
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//
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// First we must determine which interrupt register the interrupt is in.
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// Then, get the current state of the interrupt mask register. Finally,
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// set the bit corresponding to the adjusted value of Vector to zero, to
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// disable that PCI interrupt.
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//
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if ( Vector >= CORELLE_INTERRUPT2_OFFSET ) {
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//
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// The interrupt is in interrupt register 2
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//
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Vector -= CORELLE_INTERRUPT2_OFFSET;
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HalpCorellePciInterrupt2Mask =
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READ_PORT_USHORT((PUSHORT)HalpCorellePciImr2Qva );
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HalpCorellePciInterrupt2Mask |= (USHORT) (1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpCorellePciImr2Qva,
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HalpCorellePciInterrupt2Mask );
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} else {
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//
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// The interrupt is in interrupt register 1
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//
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Vector -= CORELLE_INTERRUPT1_OFFSET;
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HalpCorellePciInterrupt1Mask =
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READ_PORT_USHORT( (PUSHORT)HalpCorellePciImr1Qva );
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HalpCorellePciInterrupt1Mask |= (USHORT) (1 << Vector);
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WRITE_PORT_USHORT( (PUSHORT)HalpCorellePciImr1Qva,
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HalpCorellePciInterrupt1Mask );
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}
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}
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BOOLEAN
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HalpPciDispatch(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PKTRAP_FRAME TrapFrame
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)
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/*++
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Routine Description:
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This routine is entered as the result of an interrupt having been generated
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via the vector connected to the PCI device interrupt object. Its function
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is to call the second-level interrupt dispatch routine.
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This service routine could have been connected as follows, where the
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ISR is the assembly wrapper that does the handoff to this function:
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KeInitializeInterrupt( &Interrupt,
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HalpPciInterruptHandler,
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(PVOID) HalpPciIrQva,
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(PKSPIN_LOCK)NULL,
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PCI_VECTOR,
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PCI_DEVICE_LEVEL,
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PCI_DEVICE_LEVEL,
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LevelSensitive,
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TRUE,
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0,
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FALSE);
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KeConnectInterrupt(&Interrupt);
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Arguments:
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Interrupt - Supplies a pointer to the interrupt object.
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ServiceContext - Supplies a pointer to the PCI interrupt register.
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TrapFrame - Supplies a pointer to the trap frame for this interrupt.
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Return Value:
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Returns the value returned from the second level routine.
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--*/
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{
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UCHAR PCIVector;
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BOOLEAN returnValue;
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USHORT PCRInOffset;
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//
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// Acknowledge interrupt and receive the returned interrupt vector.
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// If we got zero back, there were no enabled interrupts, so we
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// signal that with a FALSE return, immediately.
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//
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if( HalpNoritakePlatform ) {
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PCIVector = HalpAcknowledgeNoritakePciInterrupt(ServiceContext);
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} else if ( HalpCorellePlatform ) {
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PCIVector = HalpAcknowledgeCorellePciInterrupt(ServiceContext);
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} else {
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PCIVector = HalpAcknowledgeMikasaPciInterrupt(ServiceContext);
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}
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if (PCIVector == 0) {
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return( FALSE );
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}
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PCRInOffset = PCIVector + PCI_VECTORS;
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returnValue = ((PSECONDARY_DISPATCH) PCR->InterruptRoutine[PCRInOffset])(
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PCR->InterruptRoutine[PCRInOffset],
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TrapFrame
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);
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return( returnValue );
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}
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