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446 lines
13 KiB
446 lines
13 KiB
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#ifndef _H_BBLDEF
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#define _H_BBLDEF
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#include "halp.h"
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//#include <ntos.h>
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//
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// Used for debugging
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//
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#if defined(BBL_DBG) && DBG
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#define BBL_DBG_PRINT DbgPrint
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#else
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#define BBL_DBG_PRINT
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#endif // !DBG
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//
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// Define the physical memory attribites
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//
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//#define BBL_BASE_ADDR 0xD0000000
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//#define BBL_VIDEO_MEMORY_BASE 0xD4000000
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#define BBL_VIDEO_MEMORY_OFFSET 0x04000000
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#define BBL_VIDEO_MEMORY_LENGTH 0x200000 // 2 MB
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//#define BBL_REG_ADDR_BASE 0xDA000000
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#define BBL_REG_ADDR_OFFSET 0x0A000000
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#define BBL_REG_ADDR_LENGTH 0x1000 // 4 K
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#define BBL_SCANLINE_LENGTH 0x800 // 2 K
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//
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// Define the register base
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//
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#define BBL_REG_BASE (HalpBBLRegisterBase)
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/******************************************************************************
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* *
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* Macro: BBL_SET_REG (regbase, register, data) *
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* caddr_t regbase; *
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* caddr_t register; *
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* unsigned long data; *
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* *
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* Parameters: regbase - Address of the start of the adapter address space *
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* register - Register offset of adapter register to write *
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* data - Data to write to the register *
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* *
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* Description: Writes the "data" value in the adapter register *
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* *
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* Notes: This macro may only be used by the device driver because *
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* it does not require the adapter pointer. This macro may *
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* only be called from kernel level code. *
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* *
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******************************************************************************/
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#define BBL_SET_REG(regbase, register, data) \
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(*((volatile unsigned long *) \
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((unsigned long)(regbase) | (register)))) = \
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((volatile unsigned long)(data))
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/******************************************************************************
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* *
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* Macro: BBL_GET_REG (regbase, register) *
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* caddr_t regbase; *
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* caddr_t register; *
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* *
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* Parameters: regbase - Address of the start of the adapter address space *
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* register - Register offset of adapter register to write *
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* *
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* Description: Reads the value in the adapter register *
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* *
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* Notes: This macro may only be used by the device driver because *
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* it does not require the adapter pointer. This macro may *
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* only be called from kernel level code. *
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* *
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* Returns: This macro is a RHS macro which expands to the value of *
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* the register *
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* *
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******************************************************************************/
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#define BBL_GET_REG(regbase, register) \
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(volatile unsigned long) \
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(*((volatile unsigned long *) \
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((unsigned long)(regbase) | (register))))
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/******************************************************************************
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* *
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* Macro: BBL_DD_EIEIO *
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* *
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* Parameters: None *
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* *
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* Description: This macro expands to the PowerPC assembly instruction eieio *
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* *
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* Notes: This macro compiles to an in-line assembly instruction so *
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* there is no function call overhead. The eieio instruction *
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* takes between 3 and 6 cycles on the 601 processor which *
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* amounts to 45 - 90 ns on the 66MHX 601 processor. *
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* *
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* Returns: Expands into the "eieio" in-line assembly instruction. *
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* *
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******************************************************************************/
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#define BBL_EIEIO __builtin_eieio()
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//
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// Configure the GXT150 Graphics Adapter. This function sets the
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// necessary PCI config space registers to enable the GXT150P
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// Graphics Adapter in the system for further I/O requests to it
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//
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// Standard PCI configuration register offsets
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#define PCI_DEV_VEND_ID_REG 0x00
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#define PCI_CMD_STAT_REG 0x04
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#define PCI_CMD_REG 0x04
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#define PCI_STAT_REG 0x06
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#define PCI_BASE_ADDR_REG 0x10
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// GXT150P device specific configuration register offsets
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#define BBL_DEV_CHAR_REG 0x40
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#define BBL_BUID1_REG 0x48
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#define BBL_XIVR_REG 0x60
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#define BBL_INTL_REG 0x64
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#define BBL_BELE_REG 0x70
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// GXT150P configuration register values
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#define BBL_DEV_VEND_ID 0x001B1014
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#define BBL_DEV_CHAR_VAL 0x34900040
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#define BBL_BUID1_VAL 0x00A50000
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#define BBL_XIVR_VAL 0x00000004
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#define BBL_INTL_VAL 0x0000000F
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#define BBL_BELE_VAL 0x00000008 // Little Endian Mode
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#define BBL_VEN_ID 0x1014
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#define BBL_DEV_ID 0x001b
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#define BBL_MEM_ENABLE 0x0002
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//
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// Define the monitor ID (cable and DIP switch) masks
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//
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#define BBL_MON_ID_DIP_SWITCHES_SHIFT 16
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#define BBL_MON_ID_DIP_SWITCHES_MASK \
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(0xF << BBL_MON_ID_DIP_SWITCHES_SHIFT)
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#define BBL_MON_ID_CABLE_ID_0 0x0
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#define BBL_MON_ID_CABLE_ID_H 0x1
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#define BBL_MON_ID_CABLE_ID_V 0x2
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#define BBL_MON_ID_CABLE_ID_1 0x3
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#define BBL_MON_ID_CABLE_BIT_0_SHIFT 6
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#define BBL_MON_ID_CABLE_BIT_0_MASK \
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(0x3 << BBL_MON_ID_CABLE_BIT_0_SHIFT)
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#define BBL_MON_ID_CABLE_BIT_1_SHIFT 4
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#define BBL_MON_ID_CABLE_BIT_1_MASK \
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(0x3 << BBL_MON_ID_CABLE_BIT_1_SHIFT)
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#define BBL_MON_ID_CABLE_BIT_2_SHIFT 2
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#define BBL_MON_ID_CABLE_BIT_2_MASK \
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(0x3 << BBL_MON_ID_CABLE_BIT_2_SHIFT)
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#define BBL_MON_ID_CABLE_BIT_3_SHIFT 0
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#define BBL_MON_ID_CABLE_BIT_3_MASK \
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(0x3 << BBL_MON_ID_CABLE_BIT_3_SHIFT)
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//
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// For CRT control register:
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//
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// 7 6 5 4 3 2 1 0
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// --------------------------------------------
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// | 0 | 0 | 0 | VSP | HSP | CSE | CSG | BPE |
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// --------------------------------------------
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//
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// where VPS = vert. sync polarity
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// HPS = horz. sync polarity (reversed if either CSE or CSG
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// are on for DD2 parts)
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//
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// CSE = composite sync enable on HSYNC (when enabled, bit 4 -> don't care)
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//
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// CSG = composite sync on green (when enabled, bits 4,3,2 -> don't care)
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// BPE = blanking pedistal enable
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//
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//
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// Define the monitor types
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//
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typedef struct _bbl_mon_data_t {
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ULONG monitor_id;
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#define BBL_MON_PEDISTAL_ENABLE (1L << 0)
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#define BBL_MON_COMPOSITE_SYNC_ON_GREEN (1L << 1)
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#define BBL_MON_COMPOSITE_SYNC_ON_HSYNC (1L << 2)
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#define BBL_MON_HORZ_SYNC_POLARITY_POSITIVE (1L << 3)
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#define BBL_MON_VERT_SYNC_POLARITY_POSITIVE (1L << 4)
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ULONG crt_cntl;
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ULONG x_res;
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ULONG y_res;
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ULONG frame_rate;
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ULONG pixel_freq;
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ULONG hrz_total;
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ULONG hrz_disp_end;
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ULONG hrz_sync_start;
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ULONG hrz_sync_end1;
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ULONG hrz_sync_end2;
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ULONG vrt_total;
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ULONG vrt_disp_end;
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ULONG vrt_sync_start;
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ULONG vrt_sync_end;
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#define BBL_MON_COLOR (1L << 0)
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#define BBL_MON_MONO (0L << 0)
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ULONG flags;
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} bbl_mon_data_t, *pbbl_mon_data_t;
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//
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// Set up the monitor data information
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//
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static bbl_mon_data_t bbl_mon_data[] = {
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#define BBL_MT_1 0x000200cc /* 0010 1010 */
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/* 1024x768 70Hz 78Mhz PSYNC */
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{ BBL_MT_1,
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BBL_MON_VERT_SYNC_POLARITY_POSITIVE |
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE,
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1024,768,7000,7800,
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1367,1023,1047,1327,0,
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813,767,767,775,
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BBL_MON_COLOR },
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#define BBL_MT_2 0x000a00cc /* 1010 1010 */
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/* 1280x1024 60Hz 112Mhz NSYNC */
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{ BBL_MT_2,
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0x0,
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1280,1024,6000,11200,
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1759,1279,1299,1455,1103,
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1055,1023,1026,1029,
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BBL_MON_COLOR },
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#define BBL_MT_3 0x000b00cc /* 1011 1010 */
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/* 1024x768 75.8Hz 86Mhz PSYNC */
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{ BBL_MT_3,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_VERT_SYNC_POLARITY_POSITIVE,
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1024,768,7580,8600,
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1407,1023,1031,1351,711,
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805,767,767,775,
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BBL_MON_COLOR },
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#define BBL_MT_4 0x000d00cc /* 1101 1010 */
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/* 1280x1024 77Hz 148Mhz NSYNC */
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{ BBL_MT_4,
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0x0,
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1280,1024,7700,14800,
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1819,1279,1319,1503,1115,
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1055,1023,1026,1029,
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BBL_MON_COLOR },
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#define BBL_MT_5 0x000f00cc /* 1111 1010 */
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/* 1024x768 60Hz 64Mhz NSYNC */
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{ BBL_MT_5,
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0x0,
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1024,768,6000,6400,
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1311,1023,1055,1151,991,
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812,767,770,773,
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BBL_MON_COLOR },
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#define BBL_MT_6 0x000f003f /* 1111 0111 */
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/* 1280x1024 67Hz 128Mhz NSYNC */
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{ BBL_MT_6,
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0x0,
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1280,1024,6700,12800,
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1807,1279,1351,1607,0,
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1055,1023,1023,1031,
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BBL_MON_MONO },
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#define BBL_MT_7 0x000f004c /* 1111 H010 */
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/* 1024x768 70Hz 78Mhz PSYNC */
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{ BBL_MT_7,
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BBL_MON_VERT_SYNC_POLARITY_POSITIVE |
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE,
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1024,768,7000,7800,
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1367,1023,1047,1327,0,
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813,767,767,775,
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BBL_MON_COLOR },
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#define BBL_MT_8 0x00010030 /* 0001 0100 */
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/* 1024x768 75.8Hz 86Mhz SOG */
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{ BBL_MT_8,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1024,768,7580,8600,
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1407,1023,1031,1351,711,
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805,767,767,775,
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BBL_MON_COLOR },
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#define BBL_MT_8_PATCH 0x000b0030 /* 1011 0100 */
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/* 1024x768 75.8Hz 86Mhz PSYNC */
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{ BBL_MT_8_PATCH,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_VERT_SYNC_POLARITY_POSITIVE,
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1024,768,7580,8600,
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1407,1023,1031,1351,711,
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805,767,767,775,
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BBL_MON_COLOR },
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#define BBL_MT_8_PATCH_1 0x00040030 /* 0100 0100 */
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/* 1024x768 75.8Hz 86Mhz SOG */
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{ BBL_MT_8_PATCH_1,
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BBL_MON_PEDISTAL_ENABLE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE,
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1024,768,7580,8600,
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1407,1023,1031,1231,831,
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805,767,770,778,
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BBL_MON_COLOR },
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#define BBL_MT_9 0x00020030 /* 0010 0100 */
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/* 1024x768 70Hz 75Mhz SOG */
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{ BBL_MT_9,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1024,768,7000,7500,
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1323,1023,1115,1191,1039,
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807,767,767,769,
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BBL_MON_COLOR },
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#define BBL_MT_10 0x00030030 /* 0011 0100 */
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/* 1024x768 60Hz 64Mhz SOG */
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{ BBL_MT_10,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1024,768,6000,6400,
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1311,1023,1087,1183,991,
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812,767,770,773,
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BBL_MON_COLOR },
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#define BBL_MT_11 0x00060030 /* 0110 0100 */
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/* 1280x1024 74Hz 135Mhz SOG */
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{ BBL_MT_11,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1280,1024,7400,13500,
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1711,1279,1311,1455,1167,
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1065,1023,1023,1026,
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BBL_MON_COLOR },
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#define BBL_MT_12 0x00070030 /* 0111 0100 */
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/* 1280x1024 60Hz 108Mhz SOG */
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{ BBL_MT_12,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1280,1024,6000,10800,
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1707,1279,1323,1507,1139,
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1052,1023,1026,1029,
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BBL_MON_COLOR },
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#define BBL_MT_13 0x000d0030 /* 1101 0100 */
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/* 1280x1024 77Hz 148Mhz SOG */
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{ BBL_MT_13,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1280,1024,7700,14800,
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1819,1279,1319,1503,1115,
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1055,1023,1026,1029,
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BBL_MON_COLOR },
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#define BBL_MT_14 0x000e0030 /* 1110 0100 */
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/* 1280x1024 67Hz 120Mhz SOG */
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{ BBL_MT_14,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1280,1024,6700,12000,
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1695,1279,1311,1471,1151,
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1055,1023,1026,1029,
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BBL_MON_COLOR },
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#define BBL_MT_15 0x000f0030 /* 1111 0100 */
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/* 1280x1024 60Hz 112Mhz SOG */
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{ BBL_MT_15,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_GREEN |
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BBL_MON_PEDISTAL_ENABLE,
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1280,1024,6000,11200,
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1759,1279,1299,1455,1103,
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1055,1023,1026,1029,
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BBL_MON_COLOR },
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#define BBL_MT_16 0x000f00bf /* 1111 V111 */
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/* 1280x1024 72Hz 128Mhz */
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{ BBL_MT_16,
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0x0,
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1280,1024,7200,12800,
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1687,1279,1311,1451,1167,
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1059,1023,1026,1029,
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BBL_MON_COLOR },
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#define BBL_MT_17 0x000400ff /* 0100 1111 */
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/* 1152x900 66Hz 93Mhz CSYNC */
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{ BBL_MT_17,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_HSYNC,
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1152,900,6600,9300,
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1503,1151,1179,1307,1051,
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936,899,901,905,
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BBL_MON_COLOR },
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#define BBL_MT_18 0x000500ff /* 0101 1111 */
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/* 1152x900 76Hz 106Mhz CSYNC */
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{ BBL_MT_18,
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BBL_MON_HORZ_SYNC_POLARITY_POSITIVE |
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BBL_MON_COMPOSITE_SYNC_ON_HSYNC,
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1152,900,7600,10600,
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1471,1151,1163,1259,1067,
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942,899,901,909,
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BBL_MON_COLOR },
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#define BBL_MT_DEFAULT 0x000f00ff /* 1111 1111 */
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/* THIS IS THE DEFAULT MONITOR ID */
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/* THIS IS THE NO-MONITOR ATTACHED ID */
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/* These settings are the same as BBL_MT_5 */
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/* 1024x768 60Hz 64Mhz NSYNC */
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{ BBL_MT_DEFAULT,
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0x0,
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1024,768,6000,6400,
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1311,1023,1055,1151,991,
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812,767,770,773,
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BBL_MON_COLOR },
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};
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#endif // _H_BBLDEF
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