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113 lines
4.5 KiB
113 lines
4.5 KiB
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#ifndef _H_BBLRASTZ
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#define _H_BBLRASTZ
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/******************************************************************************
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* *
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* Define the BBL rasterizer register address range: *
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* *
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******************************************************************************/
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#define BBL_REGISTER_ADDR_RANGE_START 0x0A000000
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/******************************************************************************
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* *
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* Define the BBL rasterizer register offsets: *
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* *
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******************************************************************************/
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#define BBL_CMD_DATA_REG 0x0000
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#define BBL_STATUS_REG 0x0000
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#define BBL_CNTL_REG 0x0040
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#define BBL_FG_REG 0x0044
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#define BBL_BG_REG 0x0048
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#define BBL_PLANE_MASK_REG 0x0050
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#define BBL_LINE_STYLE_DASH_1234_REG 0x0054
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#define BBL_LINE_STYLE_DASH_5678_REG 0x0058
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#define BBL_SCISSOR_ENABLE_REG 0x007C
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#define BBL_WIN_ORIGIN_OFFSETS_REG 0x0080
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#define BBL_WID_CLIP_TEST_REG 0x0084
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#define BBL_PIXEL_MASK_REG 0x00A0
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#define BBL_INTR_ENABLE_STATUS_REG 0x00B8
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#define BBL_CONFIG_REG 0x00BC
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#define BBL_RAMDAC_C0_C1_0_0_REG 0x00C0
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#define BBL_RAMDAC_C0_C1_0_1_REG 0x00C4
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#define BBL_RAMDAC_C0_C1_1_0_REG 0x00C8
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#define BBL_RAMDAC_C0_C1_1_1_REG 0x00CC
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#define BBL_RESET_CURRENT_CMD_REG 0x00D4
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/******************************************************************************
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* *
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* Define bitfields for the BBL rasterizer status register: *
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* *
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******************************************************************************/
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#define BBL_VERTICAL_RETRACE (1 << 0)
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#define BBL_ADAPTER_BUSY (1 << 2)
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#define BBL_CACHE_LINE_BUFFER_EMPTY (1 << 4)
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#define BBL_FREE_SPACE_SHIFT 16
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/******************************************************************************
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* *
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* Define the commands: *
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* *
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******************************************************************************/
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#define BBL_CMD_SHIFT 24
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#define BBL_POLYFILL_RECT_ID 0x86
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#define BBL_POLYFILL_RECT_CMD \
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(int) (BBL_POLYFILL_RECT_ID << BBL_CMD_SHIFT)
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/******************************************************************************
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* *
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* Macro: BBL_FILL_RECT (regbase, dst_x, dst_y, width, height) *
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* caddr_t regbase; *
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* short dst_x, dst_y; *
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* unsigned short width, height; *
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* *
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* Parameters: regbase - Address of the start of the adapter address space *
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* dst_x, dst_y - Screen coords of where to start the rect *
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* width, height - Dimensions of the rect *
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* *
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* Description: Performs a fill rectangle command to the adapter *
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* *
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******************************************************************************/
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#define BBL_FILL_RECT(regbase, dst_x, dst_y, width, height) \
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BBL_SET_REG((regbase), BBL_CMD_DATA_REG, \
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BBL_POLYFILL_RECT_CMD | 0x1); \
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BBL_SET_REG((regbase), BBL_CMD_DATA_REG, \
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(((unsigned short)(dst_x) << 16) | \
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(unsigned short)(dst_y))); \
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BBL_SET_REG((regbase), BBL_CMD_DATA_REG, \
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(((unsigned short)(height) << 16) | \
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(unsigned short)(width)))
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/******************************************************************************
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* *
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* Macro: BBL_BUSY_POLL (regbase) *
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* caddr_t regbase; *
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* *
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* Parameters: regbase - Address of the start of the adapter address space *
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* *
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* Description: Performs a busy poll on the adapter and returns when the *
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* adapter is no longer busy. In the case of a shallow bus *
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* interface FIFO on the adapter, this macro will also make *
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* sure that the FIFO is empty and that the adapter is not *
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* busy. This is a synchronous call. *
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* *
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******************************************************************************/
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#define BBL_BUSY_POLL(regbase) \
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while(BBL_GET_REG((regbase), BBL_STATUS_REG) & \
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BBL_ADAPTER_BUSY) \
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;
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#endif /* ! _H_BBLRASTZ */
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