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677 lines
20 KiB
677 lines
20 KiB
/*++
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Copyright (c) 1995 International Business Machines Corporation
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Module Name:
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pxs3.c
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Abstract:
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This module implements the HAL display initialization and output routines
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for a PowerPC system using an S3 video adapter.
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Author:
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Jess Botts
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "pxs3.h"
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#include "string.h"
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#include "pxvgaequ.h"
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//PHYSICAL ADDRESS of S3 video ram
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#define S3_VIDEO_MEMORY_BASE 0xC0000000
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VOID
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HalpDisplayCharacterS3 (
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IN UCHAR Character
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);
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VOID
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HalpOutputCharacterS3 (
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IN UCHAR AsciiChar
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);
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VOID
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HalpDisplayPpcS3Setup (
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VOID
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);
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// in pxdisp.c
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VOID
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WaitForVSync (
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VOID
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);
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VOID
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Scroll_Screen (
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IN UCHAR line
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);
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extern ULONG HalpInitPhase;
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extern PUCHAR HalpVideoMemoryBase;
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extern PUCHAR HalpVideoCoprocBase;
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extern ULONG HalpColumn;
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extern ULONG HalpRow;
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extern ULONG HalpHorizontalResolution;
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extern ULONG HalpVerticalResolution;
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extern USHORT HalpBytesPerRow;
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extern USHORT HalpCharacterHeight;
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extern USHORT HalpCharacterWidth;
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extern ULONG HalpDisplayText;
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extern ULONG HalpDisplayWidth;
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extern ULONG HalpScrollLength;
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extern ULONG HalpScrollLine;
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extern BOOLEAN HalpDisplayOwnedByHal;
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VOID
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HalpDisplayPpcS3Setup (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the S3 display controller chip.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Routine Description:
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//
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// This is the initialization routine for S3 86C911. This routine initializes
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// the S3 86C911 chip in the sequence of VGA BIOS for AT.
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//
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ULONG DataLong;
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USHORT i,j;
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UCHAR DataByte;
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UCHAR Index;
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// PVOID Index_3x4, Data_3x5;
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ULONG MemBase;
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PHYSICAL_ADDRESS physicalAddress;
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if (HalpInitPhase == 0) {
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HalpVideoMemoryBase = (PUCHAR)KePhase0MapIo(S3_VIDEO_MEMORY_BASE,
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0x400000); // 4 MB
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//
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// IO control space has already been mapped in phase 1 via halpmapiospace
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//
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}
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// Enable Video Subsystem
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// Accordint to chapter 5.4.2 regular VGA setup sequence
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// HalDisplayString(" Enable Video Subsystem...\n");
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WRITE_S3_UCHAR(SUBSYS_ENB, 0x10);
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// HalDisplayString(" Subsystem Enable = 0x10...\n");
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WRITE_S3_UCHAR(Setup_OP, 0x01);
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WRITE_S3_UCHAR(SUBSYS_ENB, 0x08);
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WRITE_S3_UCHAR(DAC_Mask, 0x0); // Set screen into blank
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WRITE_S3_UCHAR(Seq_Index, 0x01);
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WRITE_S3_UCHAR(Seq_Data, 0x21);
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//=========================================================================
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//
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// IBMBJB removed this section because it is not currently used, this
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// was left commented out instead of deleting it in case we use
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// a monochrome monitor in the future
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//
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// // Check monitor type to decide index address (currently not use)
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// DataByte = READ_S3_UCHAR(MiscOutR);
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// ColorMonitor = DataByte & 0x01 ? TRUE : FALSE;
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//
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// if (ColorMonitor) {
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// Index_3x4 = (PVOID)S3_3D4_Index;
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// Data_3x5 = (PVOID)S3_3D5_Data;
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// } else {
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// Index_3x4 = (PVOID)Mono_3B4;
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// Data_3x5 = (PVOID)Mono_3B5;
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// }
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//
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//=========================================================================
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//
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// -- Initialization Process Begin --
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// According to appendix B-4 "ADVANCED PROGRAMMER'S GUIDE TO THE EGA/VGA"
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// to set the default values to VGA +3 mode.
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//
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WRITE_S3_UCHAR(VSub_EnB,VideoParam[0]);
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// Note: Synchronous reset must be done before MISC_OUT write operation
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WRITE_S3_UCHAR(Seq_Index, RESET); // Synchronous Reset !
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WRITE_S3_UCHAR(Seq_Data, 0x01);
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// For ATI card(0x63) we may want to change the frequence
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WRITE_S3_UCHAR(MiscOutW,VideoParam[1]);
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// Note: Synchronous reset must be done before CLOCKING MODE register is
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// modified
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WRITE_S3_UCHAR(Seq_Index, RESET); // Synchronous Reset !
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WRITE_S3_UCHAR(Seq_Data, 0x01);
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// Sequencer Register
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for (Index = 1; Index < 5; Index++) {
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WRITE_S3_UCHAR(Seq_Index, Index);
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WRITE_S3_UCHAR(Seq_Data, VideoParam[SEQ_OFFSET+Index]);
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}
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#ifdef POLO // if compiling for a Polo
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WRITE_S3_UCHAR(S3_3D4_Index, S3R0);
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DataByte = READ_S3_UCHAR(S3_3D5_Data);
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if((DataByte & 0xf0) == 0xc0) { // if display adaptor is an S3 864
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WRITE_S3_UCHAR(Seq_Index, 0x01);
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DataByte = READ_S3_UCHAR(Seq_Data);
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DataByte |= 0x01; // use an 8 dot character clock
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WRITE_S3_UCHAR(Seq_Data, DataByte);
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}
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#endif
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// Set CRT Controller
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// out 3D4, 0x11, 00 (bit 7 must be 0 to unprotect CRT R0-R7)
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// UnLockCR0_7();
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WRITE_S3_UCHAR(S3_3D4_Index, VERTICAL_RETRACE_END);
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DataByte = READ_S3_UCHAR(S3_3D5_Data);
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DataByte = DataByte & 0x7f;
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WRITE_S3_UCHAR(S3_3D5_Data, DataByte);
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// CRTC controller CR0 - CR18
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for (Index = 0; Index < 25; Index++) {
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WRITE_S3_UCHAR(S3_3D4_Index, Index);
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WRITE_S3_UCHAR(S3_3D5_Data, VideoParam[CRT_OFFSET+Index]);
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}
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// attribute write
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// program palettes and mode register
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// HalDisplayString(" Program palettes ...\n");
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for (Index = 0; Index < 21; Index++) {
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WaitForVSync();
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DataByte = READ_S3_UCHAR(Stat1_In); // Initialize Attr. F/F
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WRITE_S3_UCHAR(Attr_Index,Index);
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KeStallExecutionProcessor(5);
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WRITE_S3_UCHAR(Attr_Data,VideoParam[ATTR_OFFSET+Index]);
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KeStallExecutionProcessor(5);
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WRITE_S3_UCHAR(Attr_Index,0x20); // Set into normal operation
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}
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WRITE_S3_UCHAR(Seq_Index, RESET); // reset to normal operation !
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WRITE_S3_UCHAR(Seq_Data, 0x03);
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// graphics controller
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// HalDisplayString(" Graphics controller...\n");
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for (Index = 0; Index < 9; Index++) {
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WRITE_S3_UCHAR(GC_Index, Index);
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WRITE_S3_UCHAR(GC_Data, VideoParam[GRAPH_OFFSET+Index]);
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}
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// turn off the text mode cursor
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WRITE_S3_UCHAR(S3_3D4_Index, CURSOR_START);
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WRITE_S3_UCHAR(S3_3D5_Data, 0x2D);
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// Unlock S3 specific registers
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WRITE_S3_UCHAR(S3_3D4_Index, S3R8);
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WRITE_S3_UCHAR(S3_3D5_Data, 0x48);
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// Unlock S3 SC registers
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WRITE_S3_UCHAR(S3_3D4_Index, S3R9);
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WRITE_S3_UCHAR(S3_3D5_Data, 0xa0);
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// Disable enhanced mode
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WRITE_S3_UCHAR(ADVFUNC_CNTL, 0x02);
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// Turn off H/W Graphic Cursor
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WRITE_S3_UCHAR(S3_3D4_Index, SC5);
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WRITE_S3_UCHAR(S3_3D5_Data, 0x0);
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//=========================================================================
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//
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// IBMBJB S3 errata sheet says that CR40 can not be read correctly after
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// power up until it has been written to, suggested workaround is
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// to use the power on default (0xA4) Since the intent of the
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// existing code was to reset bit 0, 0xA4 will be used to reset
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// the bit. The other bits that are reset select the desired
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// default configuration.
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//
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// If this register is written by the firmware then this fix is
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// unneccessary. If future modifications of the firmware were to
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// remove all writes to this register then this fix would have to
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// be added here. This is being added now to protect this code
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// from possible firmware changes.
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//
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// // Disable enhanced mode registers access
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// WRITE_S3_UCHAR(S3_3D4_Index, SC0);
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// DataByte = READ_S3_UCHAR(S3_3D5_Data);
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// DataByte &= 0xfe;
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// DataByte ^= 0x0;
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//
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// WRITE_S3_UCHAR(S3_3D5_Data, DataByte);
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//
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WRITE_S3_UCHAR( S3_3D4_Index, SC0 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0xA4 );
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//=========================================================================
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// Set Misc 1 register
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WRITE_S3_UCHAR(S3_3D4_Index, S3R0A);
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DataByte = READ_S3_UCHAR(S3_3D5_Data);
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DataByte &= 0xc7;
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DataByte ^= 0x0;
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WRITE_S3_UCHAR(S3_3D5_Data, DataByte);
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// Set S3R1 register
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WRITE_S3_UCHAR(S3_3D4_Index, S3R1);
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DataByte = READ_S3_UCHAR(S3_3D5_Data);
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DataByte &= 0x80;
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DataByte ^= 0x0;
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WRITE_S3_UCHAR(S3_3D5_Data, DataByte);
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// Set S3R2 register
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WRITE_S3_UCHAR(S3_3D4_Index, S3R2);
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WRITE_S3_UCHAR(S3_3D5_Data, 0x0);
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// Set S3R4 register
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WRITE_S3_UCHAR(S3_3D4_Index, S3R4);
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DataByte = READ_S3_UCHAR(S3_3D5_Data);
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DataByte &= 0xec;
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DataByte ^= 0x0;
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WRITE_S3_UCHAR(S3_3D5_Data, DataByte);
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//=========================================================================
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//
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// IBMBJB added this section to eliminate the DAC hardware cursor, this
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// is done before setting registers 0x50 - 0x62 to default states
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// so that R55's default state will not be undone.
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//
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// this sequence zeros the 2 least signifigant bits in command
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// register 2 on the DAC
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WRITE_S3_UCHAR( S3_3D4_Index, 0x55 ); // set RS[3:2] to 10
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DataByte = READ_S3_UCHAR( S3_3D5_Data );
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DataByte &= 0xfc;
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DataByte |= 0x02;
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WRITE_S3_UCHAR( S3_3D5_Data, DataByte );
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DataByte = READ_S3_UCHAR( DAC_Data );
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DataByte &= 0xfc; // zero CR21,20 in DAC command
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WRITE_S3_UCHAR( DAC_Data, DataByte ); // register 2
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//=========================================================================
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//
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// IBMBJB Added code to configure for 18 bit color mode and reload the
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// palette registers because the firmware configures for 24 bit
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// color. If this is done when the system driver initializes for
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// graphics mode then the text mode colors can not be changed
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// properly.
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WRITE_S3_UCHAR( S3_3D4_Index, 0x55 ); // RS[3:2] = 01B to address
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WRITE_S3_UCHAR( S3_3D5_Data, 0x01 ); // DAC command register 0
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DataByte = READ_S3_UCHAR( DAC_Mask ); // reset bit 1 in DAC command
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DataByte &= 0xfd; // register 0 to select 6 bit
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WRITE_S3_UCHAR( DAC_Mask, DataByte ); // operation (18 bit color)
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// IBMBJB added write to SDAC PLL control register to make sure CLK0
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// is correct if we have to reinitialize after graphics mode
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// initialization, this does not bother the 928/Bt485 card
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// because the Bt485 DAC looks very much like the SDAC
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WRITE_S3_UCHAR( DAC_WIndex, 0x0e ); // select SDAC PLL control reg
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WRITE_S3_UCHAR( DAC_Data, 0x00 ); // select SDAC CLK0
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WRITE_S3_UCHAR( S3_3D4_Index, 0x55 ); // select DAC color palette
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 ); // registers
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WRITE_S3_UCHAR( DAC_WIndex, 0 ); // start load in register 0
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for( i = 0, j = 0; i < 256; ++i ) // load all color registers
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{
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WRITE_S3_UCHAR( DAC_Data, TextPalette[j++] ); // red intensity
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WRITE_S3_UCHAR( DAC_Data, TextPalette[j++] ); // green intensity
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WRITE_S3_UCHAR( DAC_Data, TextPalette[j++] ); // blue intensity
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}
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//=========================================================================
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//
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// IBMBJB added writes to registers 0x50 - 0x62 to set them to a known
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// state because some of them are set by the firmware and are
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// not correct for our use
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//
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// NOTE: there are some writes to the DAC registers in code that
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// executes later that depend on R55[1:0] being 00B, if the
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// default state of R55 is changed make sure that these bits
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// are not changed
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WRITE_S3_UCHAR( S3_3D4_Index, 0x50 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x51 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x52 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x53 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x54 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x55 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x56 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x57 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x58 );
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#ifdef SAM_256
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WRITE_S3_UCHAR( S3_3D5_Data, 0x40 );
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#else
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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#endif
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WRITE_S3_UCHAR( S3_3D4_Index, 0x59 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x5a );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x0a );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x5B );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x5C );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x5D );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x5E );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x5F );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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// IBMBJB changed value written from 0 to 1 for an S3 864 based card to
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// clear up bad display caused by 864->SDAC FIFO underrun
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WRITE_S3_UCHAR( S3_3D4_Index, 0x60 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x01 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x61 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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WRITE_S3_UCHAR( S3_3D4_Index, 0x62 );
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WRITE_S3_UCHAR( S3_3D5_Data, 0x00 );
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//=========================================================================
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//
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// IBMBJB added setting bits 7 and 6 of CR65, errata sheet fix for split
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// transfer problem in parallel and continuous addressing modes
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// Note: side effect of setting bit 7 was a garbled firmware screen after
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// shutdown.
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// Set SR65 bits 7 and 6
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WRITE_S3_UCHAR(S3_3D4_Index, 0x65);
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DataByte = READ_S3_UCHAR(S3_3D5_Data);
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DataByte |= 0x40;
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// DataByte |= 0xc0;
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WRITE_S3_UCHAR(S3_3D5_Data, DataByte);
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// Lock S3 SC registers
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WRITE_S3_UCHAR(S3_3D4_Index, S3R9);
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WRITE_S3_UCHAR(S3_3D5_Data, 0x0);
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// Lock S3 specific registers
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WRITE_S3_UCHAR(S3_3D4_Index, S3R8);
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WRITE_S3_UCHAR(S3_3D5_Data, 0x0);
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// Load character fonts into plane 2 (A0000-AFFFF)
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// HalDisplayString(" Load Fonts into Plane2 ...\n");
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WRITE_S3_UCHAR(Seq_Index,0x02); // Enable Write Plane reg
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WRITE_S3_UCHAR(Seq_Data,0x04); // select plane 2
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WRITE_S3_UCHAR(Seq_Index,0x04); // Memory Mode Control reg
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WRITE_S3_UCHAR(Seq_Data,0x06); // access to all planes,
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WRITE_S3_UCHAR(GC_Index,0x05); // Graphic, Control Mode reg
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WRITE_S3_UCHAR(GC_Data,0x00);
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WRITE_S3_UCHAR(GC_Index,0x06);
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WRITE_S3_UCHAR(GC_Data,0x04);
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|
WRITE_S3_UCHAR(GC_Index,0x04);
|
|
WRITE_S3_UCHAR(GC_Data,0x02);
|
|
|
|
|
|
MemBase = 0xA0000;
|
|
for (i = 0; i < 256; i++) {
|
|
for (j = 0; j < 16; j++) {
|
|
WRITE_S3_VRAM(MemBase, VGAFont8x16[i*16+j]);
|
|
MemBase++;
|
|
}
|
|
// 32 bytes each character font
|
|
for (j = 16; j < 32; j++) {
|
|
WRITE_S3_VRAM(MemBase, 0 );
|
|
MemBase++;
|
|
}
|
|
}
|
|
|
|
// turn on screen
|
|
WRITE_S3_UCHAR(Seq_Index, 0x01);
|
|
DataByte = READ_S3_UCHAR(Seq_Data);
|
|
DataByte &= 0xdf;
|
|
DataByte ^= 0x0;
|
|
WRITE_S3_UCHAR(Seq_Data, DataByte);
|
|
|
|
WaitForVSync();
|
|
|
|
// Enable all the planes through the DAC
|
|
WRITE_S3_UCHAR(DAC_Mask, 0xff);
|
|
|
|
// select plane 0, 1
|
|
WRITE_S3_UCHAR(Seq_Index, 0x02); // Enable Write Plane reg
|
|
WRITE_S3_UCHAR(Seq_Data, VideoParam[SEQ_OFFSET+0x02]);
|
|
|
|
// access to planes 0, 1.
|
|
WRITE_S3_UCHAR(Seq_Index, 0x04); // Memory Mode Control reg
|
|
WRITE_S3_UCHAR(Seq_Data, VideoParam[SEQ_OFFSET+0x04]);
|
|
|
|
WRITE_S3_UCHAR(GC_Index, 0x05); // Graphic, Control Mode reg
|
|
WRITE_S3_UCHAR(GC_Data, VideoParam[GRAPH_OFFSET+0x05]);
|
|
|
|
WRITE_S3_UCHAR(GC_Index, 0x04);
|
|
WRITE_S3_UCHAR(GC_Data, VideoParam[GRAPH_OFFSET+0x04]);
|
|
|
|
WRITE_S3_UCHAR(GC_Index, 0x06);
|
|
WRITE_S3_UCHAR(GC_Data, VideoParam[GRAPH_OFFSET+0x06]);
|
|
|
|
//
|
|
// Set screen into blue
|
|
//
|
|
// HalDisplayString(" Set Screen into Blue ...\n");
|
|
for (DataLong = 0xB8000; DataLong < 0xB8FA0; DataLong += 2) {
|
|
WRITE_S3_VRAM(DataLong, 0x20);
|
|
WRITE_S3_VRAM(DataLong+1, 0x1F);
|
|
}
|
|
// End of initialize S3 standard VGA +3 mode
|
|
|
|
//
|
|
// Initialize the current display column, row, and ownership values.
|
|
//
|
|
|
|
HalpColumn = 0;
|
|
HalpRow = 0;
|
|
//IBMLAN===============================================================
|
|
// Added the following so that HalQueryDisplayParameters() and
|
|
// HalSetDisplayParameters() work with either S3 or P9.
|
|
HalpDisplayWidth = 80;
|
|
HalpDisplayText = 25;
|
|
HalpScrollLine = 160;
|
|
HalpScrollLength =
|
|
HalpScrollLine * (HalpDisplayText - 1);
|
|
|
|
//end IBMLAN===========================================================
|
|
HalpDisplayOwnedByHal = TRUE;
|
|
|
|
return;
|
|
} /* end of HalpDisplayPpcS3Setup() */
|
|
|
|
VOID
|
|
HalpDisplayCharacterS3 (
|
|
IN UCHAR Character
|
|
)
|
|
|
|
/*++
|
|
Routine Description:
|
|
|
|
This routine displays a character at the current x and y positions in
|
|
the frame buffer. If a newline is encounter, then the frame buffer is
|
|
scrolled. If characters extend below the end of line, then they are not
|
|
displayed.
|
|
|
|
Arguments:
|
|
|
|
Character - Supplies a character to be displayed.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
|
|
//
|
|
// If the character is a newline, then scroll the screen up, blank the
|
|
// bottom line, and reset the x position.
|
|
//
|
|
|
|
if (Character == '\n') {
|
|
HalpColumn = 0;
|
|
if (HalpRow < (HalpDisplayText - 1)) {
|
|
HalpRow += 1;
|
|
} else { // need to scroll up the screen
|
|
Scroll_Screen(1);
|
|
}
|
|
}
|
|
|
|
else if( Character == '\t' ) // tab?
|
|
{
|
|
HalpColumn += TAB_SIZE;
|
|
HalpColumn = (HalpColumn / TAB_SIZE) * TAB_SIZE;
|
|
|
|
if( HalpColumn >= HalpDisplayWidth ) // tab beyond end of screen?
|
|
{
|
|
HalpColumn = 0; // next tab stop is 1st column of next line
|
|
|
|
if( HalpRow >= (HalpDisplayText - 1) )
|
|
Scroll_Screen( 1 ); // scroll the screen up
|
|
else
|
|
++HalpRow;
|
|
}
|
|
}
|
|
|
|
else if (Character == '\r') {
|
|
HalpColumn = 0;
|
|
} else if (Character == 0x7f) { /* DEL character */
|
|
if (HalpColumn != 0) {
|
|
HalpColumn -= 1;
|
|
HalpOutputCharacterS3(0);
|
|
HalpColumn -= 1;
|
|
} else /* do nothing */
|
|
;
|
|
} else if (Character >= 0x20) {
|
|
// Auto wrap for 80 columns per line
|
|
if (HalpColumn >= HalpDisplayWidth) {
|
|
HalpColumn = 0;
|
|
if (HalpRow < (HalpDisplayText - 1)) {
|
|
HalpRow += 1;
|
|
} else { // need to scroll up the screen
|
|
Scroll_Screen(1);
|
|
}
|
|
}
|
|
HalpOutputCharacterS3(Character);
|
|
} else /* skip the nonprintable character */
|
|
;
|
|
|
|
return;
|
|
|
|
} /* end of HalpDisplayCharacterS3() */
|
|
|
|
|
|
VOID
|
|
HalpOutputCharacterS3 (
|
|
IN UCHAR AsciiChar
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine insert a set of pixels into the display at the current x
|
|
cursor position. If the x cursor position is at the end of the line,
|
|
then no pixels are inserted in the display.
|
|
|
|
Arguments:
|
|
|
|
Character - Supplies a character to be displayed.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG I;
|
|
|
|
//
|
|
// If the current x cursor position is within the current line, then insert
|
|
// the specified pixels into the last line of the text area and update the
|
|
// x cursor position.
|
|
//
|
|
if (HalpColumn < HalpDisplayWidth) {
|
|
I = (HalpRow*HalpScrollLine+HalpColumn*2);
|
|
WRITE_S3_VRAM(0xb8000 + I, AsciiChar);
|
|
|
|
HalpColumn += 1;
|
|
} else // could expand to automatic wrap line. 9/9/92 By Andrew
|
|
;
|
|
|
|
return;
|
|
} /* end of HalpOutputCharacterS3() */
|
|
|
|
|