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280 lines
7.1 KiB
280 lines
7.1 KiB
/*++
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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sableref.h
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Abstract:
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This file defines the structures and definitions describing the
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basic Sable family IO structure. These definitions are common to
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all sable family systems (Sable, Gamma, Lynx...)
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Author:
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Steve Brooks 28-Dec 1994
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef _SABLEREFH_
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#define _SABLEREFH_
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//
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// Define QVA constants for SABLE.
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//
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#if !defined(QVA_ENABLE)
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#define QVA_ENABLE (0xA0000000) // Identify VA as a QVA
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#endif //QVA_ENABLE
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#define QVA_SELECTORS (0xE0000000) // QVA identification mask
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#define IO_BIT_SHIFT 0x05 // Bits to shift QVA
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#define IO_BYTE_OFFSET 0x20 // Offset to next byte
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#define IO_SHORT_OFFSET 0x40 // Offset to next short
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#define IO_LONG_OFFSET 0x80 // Offset to next long
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#define IO_QUAD_OFFSET 0x100 // Offset to next quad
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#define IO_BYTE_LEN 0x00 // Byte length
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#define IO_WORD_LEN 0x08 // Word length
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#define IO_TRIBYTE_LEN 0x10 // TriByte length
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#define IO_LONG_LEN 0x18 // Longword length
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//
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// Define size of I/O and memory space for Sable
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// Assume that the HAE==0. This reduces the maximum space from
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// 4Gbytes to 128Mbytes.
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//
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#define PCI0_MAX_IO_ADDRESS ((16*1024*1024) - 1)
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#define PCI0_MAX_SPARSE_MEMORY_ADDRESS ((128*1024*1024) - 1)
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#define PCI0_MIN_DENSE_MEMORY_ADDRESS (PCI0_MAX_SPARSE_MEMORY_ADDRESS + 1)
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#define PCI0_MAX_DENSE_MEMORY_ADDRESS (__1GB - 1)
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//
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// Definitions for 64Bit PCI Bus (PCI 1)
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//
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#define PCI1_MAX_SPARSE_IO_ADDRESS ((16*1024*1024) - 1)
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#define PCI1_MAX_SPARSE_MEMORY_ADDRESS ((64*1024*1024) - 1)
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#define PCI1_MIN_DENSE_MEMORY_ADDRESS (PCI1_MAX_SPARSE_MEMORY_ADDRESS + 1)
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#define PCI1_MAX_DENSE_MEMORY_ADDRESS (__1GB - 1)
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//
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// The following constants define the base QVA's for Sables
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// PCI dense spaces. The bus address is used as an offset into this space.
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//
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#define SABLE_PCI0_DENSE_MEMORY_QVA 0xc0000000
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#define SABLE_PCI1_DENSE_MEMORY_QVA 0x00000000
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// Highest Virtual local PCI Slot is 10 == PCI_AD[21]
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#define PCI_MAX_LOCAL_DEVICE 10
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//
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// Define physical processor numbers:
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//
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#define SABLE_CPU0 0
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#define SABLE_CPU1 1
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#define SABLE_CPU2 2
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#define SABLE_CPU3 3
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#if !defined(_LANGUAGE_ASSEMBLY)
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//
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// PCI CONFIG_ADDRESS configuration space offsets for Sable PCI devices
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// These are CPU address bit masks, shifted to set in a QVA.
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// PCI
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// IDSEL
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// -----
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#define PCI0_SCSI_HEADER_OFFSET (0x00020000 >> IO_BIT_SHIFT) // AD[12]
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#define PCI0_EISA_BRIDGE_HEADER_OFFSET (0x00040000 >> IO_BIT_SHIFT) // AD[13]
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#define PCI0_SLOT_0_HEADER_OFFSET (0x00400000 >> IO_BIT_SHIFT) // AD[17]
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#define PCI0_SLOT_1_HEADER_OFFSET (0x00800000 >> IO_BIT_SHIFT) // AD[18]
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//
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// Define the values for the Eisa/Isa bus interrupt levels.
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//
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typedef enum _SABLE_EISA_BUS_LEVELS{
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EisaInterruptLevel3 = 3,
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EisaInterruptLevel4 = 4,
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EisaInterruptLevel5 = 5,
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EisaInterruptLevel6 = 6,
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EisaInterruptLevel7 = 7,
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EisaInterruptLevel9 = 9,
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EisaInterruptLevel10 = 10,
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EisaInterruptLevel11 = 11,
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EisaInterruptLevel12 = 12,
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EisaInterruptLevel14 = 14,
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EisaInterruptLevel15 = 15
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} SABLE_EISA_BUS_LEVELS, *PSABLE_EISA_BUS_LEVELS;
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//
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// N.B. The structure below defines the address offsets of the control
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// registers when used with the base QVA. It does NOT define the
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// size or structure of the individual registers.
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//
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typedef struct _SABLE_EDGE_LEVEL_CSRS{
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UCHAR EdgeLevelControl1;
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UCHAR EdgeLevelControl2;
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} SABLE_EDGE_LEVEL_CSRS, *PSABLE_EDGE_LEVEL_CSRS;
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typedef struct _SABLE_EDGE_LEVEL1_MASK{
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UCHAR Irq3 : 1;
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UCHAR Irq4 : 1;
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UCHAR Irq5 : 1;
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UCHAR Irq6 : 1;
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UCHAR Irq7 : 1;
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UCHAR Irq9 : 1;
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UCHAR Irq10 : 1;
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UCHAR Irq11 : 1;
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} SABLE_EDGE_LEVEL1_MASK, *PSABLE_EDGE_LEVEL1_MASK;
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typedef struct _SABLE_EDGE_LEVEL2_MASK{
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UCHAR Irq12 : 1;
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UCHAR Irq14 : 1;
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UCHAR Irq15 : 1;
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UCHAR Reserved : 4;
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UCHAR Sab : 1;
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} SABLE_EDGE_LEVEL2_MASK, *PSABLE_EDGE_LEVEL2_MASK;
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typedef struct _SABLE_INTERRUPT_CSRS{
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UCHAR InterruptAcknowledge;
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UCHAR Filler0;
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UCHAR MasterControl;
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UCHAR MasterMask;
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UCHAR Slave0Control;
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UCHAR Slave0Mask;
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UCHAR Filler1;
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UCHAR Filler2;
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UCHAR Slave1Control;
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UCHAR Slave1Mask;
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UCHAR Slave2Control;
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UCHAR Slave2Mask;
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UCHAR Slave3Control;
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UCHAR Slave3Mask;
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} SABLE_INTERRUPT_CSRS, *PSABLE_INTERRUPT_CSRS;
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//
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// The Sable interrupt vectors are allocated to make dispatching code
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// as efficient as possible. The bits in the 8 bit vector are broken
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// into two fields (sssssooo):
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//
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// sssss - value that selects the slave
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// 0000x = Non-PIC interrupts (always the first 16 vectors)
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// 00010 = Master
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// 00100 = Slave 0
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// 01000 = Slave 1
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// 10000 = Slave 2
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// 10001 = Slave 3
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// ooo - vector offset for the slave
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//
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typedef enum _SABLE_INTERRUPT_VECTORS {
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MasterBaseVector = 0x10,
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MasterVector0 = 0x10,
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Slave0CascadeVector,
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MasterVector2,
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Slave1CascadeVector,
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Slave2CascadeVector,
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Slave3CascadeVector,
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MasterVector6,
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MasterVector7,
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MasterPassiveVector = 0x17,
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Slave0BaseVector = 0x20,
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PciSlot0AVector = 0x20,
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ScsiPortVector,
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EthernetPortVector,
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MouseVector,
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PciSlot1AVector,
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PciSlot2AVector,
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KeyboardVector,
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FloppyVector,
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Slave0PassiveVector = 0x27,
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Slave1BaseVector = 0x40,
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SerialPort1Vector = 0x40,
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ParallelPortVector,
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EisaIrq3Vector,
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EisaIrq4Vector,
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EisaIrq5Vector,
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EisaIrq6Vector,
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EisaIrq7Vector,
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SerialPort0Vector,
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Slave1PassiveVector = 0x47,
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Slave2BaseVector = 0x80,
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EisaIrq9Vector = 0x80,
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EisaIrq10Vector,
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EisaIrq11Vector,
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EisaIrq12Vector,
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PciSlot2BVector,
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EisaIrq14Vector,
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EisaIrq15Vector,
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I2cVector,
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Slave2PassiveVector = 0x87,
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Slave3BaseVector = 0x88,
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PciSlot0BVector = 0x88,
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PciSlot1BVector,
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PciSlot0CVector,
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PciSlot1CVector,
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PciSlot2CVector,
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PciSlot0DVector,
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PciSlot1DVector,
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PciSlot2DVector,
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Slave3PassiveVector = 0x8F,
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MaximumSableVector
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} SABLE_INTERRUPT_VECTORS, *PSABLE_INTERRUPT_VECTORS;
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#define SlaveVectorMask (Slave0BaseVector | Slave1BaseVector | Slave2BaseVector | Slave3BaseVector)
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//
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// Define the position of the interrupt vectors within the
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// InterruptDispatchTable.
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//
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#define SABLE_VECTORS 0x20
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#define SABLE_VECTORS_MAXIMUM (SABLE_VECTORS + MaximumSableVector)
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// Highest PCI interrupt vector is in Sable Vector Space
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#define PCI_MAX_INTERRUPT_VECTOR MaximumSableVector
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//
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// Definitions for the old Standard I/O board (before
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// the 5th (Slave 3) 8259 was added to break out the
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// individual PCI A,B,C,D interrupt pins.
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//
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#define OldSlaveVectorMask (Slave0BaseVector | Slave1BaseVector | Slave2BaseVector)
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#define OldPciSlot0Vector PciSlot0AVector
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#define OldPciSlot1Vector PciSlot1AVector
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#define OldPciSlot2Vector PciSlot2AVector
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#endif // _LANGUAGE_ASSEMBLY
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#endif // _SABLEREFH_
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