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143 lines
3.4 KiB
143 lines
3.4 KiB
/*++ BUILD Version: 0001 // Increment this if a change has global effects
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Copyright (c) 1996 International Business Machines Corporation
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Module Name:
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pxmemctl.h
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Abstract:
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This header file defines the structures for the planar registers
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for an Idaho memory controller.
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Author:
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Jim Wooldridge
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Revision History:
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Peter L Johnston ([email protected]) August 1995.
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Doral.
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--*/
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//
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// define physical base addresses of planar registers (non UNION)
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//
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#define INTERRUPT_PHYSICAL_BASE 0xbffffff0 // physical base of interrupt source
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#define ERROR_ADDRESS_REGISTER 0xbfffeff0
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//
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// define physical base addresses of UNION planar registers
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//
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//
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// 8259 Interrupt Source (DORAL)
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//
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#define UNION_INTERRUPT_PHYSICAL_BASE 0xbfff7700
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//
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// IO Space (ISA)
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//
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#define IO_CONTROL_PHYSICAL_BASE 0x80000000
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//
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// UNION System Control Registers
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//
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#define UNION_SYSTEM_CONTROL_REG_BASE 0xff001000
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//
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// System Error Control Register (offset from UNION_SYSTEM_CONTROL_REG_BASE)
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//
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#define UNION_SECR 0x50
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//
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// System Error Status Register (offset)
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//
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#define UNION_SESR 0x60
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//
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// System Error Address Register (offset)
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//
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#define UNION_SEAR 0x70
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//
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// Memory Error Status Register (offset)
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//
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#define UNION_MESR 0x120
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//
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// Memory Error Address Register (offset)
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//
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#define UNION_MEAR 0x130
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//
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// System Error Status Register bit definitions.
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//
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// Reserved 0xe0000000
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#define UNION_SESR_CHECKSTOP 0x20000000
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#define UNION_SESR_FLASH_WRITE 0x10000000
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#define UNION_SESR_IGMC_ACCESS 0x08000000
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#define UNION_SESR_DISABLED_ADDRESS 0x04000000
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// Reserved 0x03f00000
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#define UNION_SESR_T1_ACCESS 0x00080000
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#define UNION_SESR_ADDRESS_BUS_PARITY 0x00040000
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#define UNION_SESR_DATA_BUS_PARITY 0x00020000
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#define UNION_SESR_NO_L2_HIT_ACCESS 0x00010000
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#define UNION_SESR_CPU_TO_PCI_ACCESS 0x00008000
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#define UNION_SESR_PCI32_BUS_MASTER 0x00004000
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#define UNION_SESR_PCI64_BUS_MASTER 0x00002000
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#define UNION_SESR_XFERDATA 0x00001000
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#define UNION_SESR_DATA_BUS_TIMEOUT 0x00000800
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#define UNION_SESR_CPU_MEMORY_ACCESS 0x00000400
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// Reserved 0x000003ff
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//
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// Bits 17, 18 and 19 above represent PCI initiated errors and
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// the System Error Address Register is not updated. In these
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// cases the PCI bridges or xferdata logic must be interogated
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// to determine the cause of the error. Bit 16 also requires
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// bridge interrogation.
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//
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#define UNION_SEAR_NOT_SET (UNION_SESR_PCI32_BUS_MASTER | \
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UNION_SESR_PCI64_BUS_MASTER | \
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UNION_SESR_XFERDATA)
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//
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// Memory Error Status Register bit definitions
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//
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#define UNION_MESR_DOUBLE_BIT 0x80000000
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#define UNION_MESR_SINGLE_BIT 0x40000000
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#define UNION_MESR_ADDRESS 0x20000000
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#define UNION_MESR_OVERLAPPED_MEM_EXT 0x10000000
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//reserved 0x0fffff00
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#define UNION_MESR_SYNDROME 0x000000ff
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//
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// UNION Channel Status Register is at offset 0x1800 from the PCI Config
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// Address register. Processor Load/Store Status Register is at offset
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// 0x1810.
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//
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#define UNION_PCI_CSR_OFFSET 0x1800
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#define UNION_PCI_PLSSR_OFFSET 0x1810
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