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745 lines
16 KiB
745 lines
16 KiB
/******************************************************************************
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Copyright (c) 1994 IBM Corporaion
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wdvga.c
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This module is a modification of the HAL display initialization and output
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routines for IBM Woodfield WD90C24A Graphics system. This version of wdvga.c
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is intended to be used by the OS loader to provide putc capabilities with
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the WD card.
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This file was created by copying s3vga.c and modifying it to remove
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everything except the code that initializes the VGA common registers.
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Author:
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Hiroshi Itoh 25-Feb-1994
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Revision History:
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******************************************************************************/
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#define USE_VGA_PALETTE 1
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# include "halp.h"
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# include "pvgaequ.h"
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# include "wdvga.h"
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/*****************************************************************************/
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// +++++++ IBM BJB added PCI bus definitions and tab size definition
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// PCI slot configuration space addresses
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# define UPPER_PCI_SLOT 0x80804000L
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# define LOWER_PCI_SLOT 0x80802000L
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# define PCI_BASE UPPER_PCI_SLOT
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// PCI configuration space record offsets
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# define VENDOR_ID 0x00
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# define DEVICE_ID 0x02
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# define COMMAND 0X04
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# define DEVICE_STATUS 0X06
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# define REVISION_ID 0x08
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# define PROG_INTERFACE 0x0a
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# define BASE_MEM_ADDRESS 0x10
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# define TAB_SIZE 4
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/*****************************************************************************/
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//
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// Define forward referenced procedure prototypes.
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//
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VOID
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InitializeWD (
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VOID
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);
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BOOLEAN WDIsPresent (
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VOID
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);
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VOID
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SetWDVGAConfig (
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VOID
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);
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VOID
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LockPR (
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USHORT,
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PUCHAR
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);
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VOID
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UnlockPR (
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USHORT,
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PUCHAR
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);
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VOID
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RestorePR (
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USHORT,
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PUCHAR
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);
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//
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// Define paradise registers setting variation
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//
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#define pr72_alt (pr72 | 0x8000) // avoid pr30 index conflict
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#define pr1b_ual (pr1b) // pr1b unlock variation
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#define pr1b_ush (pr1b | 0x4000) // pr1b unlock variation
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#define pr1b_upr (pr1b | 0x8000) // pr1b unlock variation
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//
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// Define static data (in s3vga.c)
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//
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extern
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ULONG
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Row,
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Column,
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ScrollLine,
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DisplayText;
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/******************************************************************************
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This routine initializes the WD display controller chip.
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This is the initialization routine for WD90C24A2. This routine initializes
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the WD90C24A2 chip in the sequence of VGA BIOS.
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******************************************************************************/
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VOID
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InitializeWD( VOID )
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{
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ULONG DataLong;
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USHORT i, j;
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UCHAR DataByte;
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UCHAR Index;
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PVOID Index_3x4, Data_3x5;
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ULONG MemBase;
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// these lines were moved to here from the original jxdisp.c
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// routine that called this one
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//
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// In the HAL, we just put the video card into text mode.
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DisplayText = 25;
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ScrollLine = 160;
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// Enable Video Subsystem according to the WD90C24 reference book
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WRITE_WD_UCHAR( SUBSYS_ENB, 0x16 );
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WRITE_WD_UCHAR( Setup_OP, 0x01 );
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WRITE_WD_UCHAR( SUBSYS_ENB, 0x0e );
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WRITE_WD_UCHAR( VSub_EnB, VideoParam[0] );
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SetWDVGAConfig();
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// Note: Synchronous reset must be done before MISC_OUT write operation
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WRITE_WD_UCHAR( Seq_Index, RESET ); // Synchronous Reset !
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WRITE_WD_UCHAR( Seq_Data, 0x01 );
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// For ATI card (0x63) we may want to change the frequence
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WRITE_WD_UCHAR( MiscOutW, VideoParam[1] );
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// Note: Synchronous reset must be done before CLOCKING MODE register is
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// modified
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WRITE_WD_UCHAR( Seq_Index, RESET ); // Synchronous Reset !
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WRITE_WD_UCHAR( Seq_Data, 0x01 );
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// Sequencer Register
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for( Index = 1; Index < 5; Index++ )
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{
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WRITE_WD_UCHAR( Seq_Index, Index );
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WRITE_WD_UCHAR( Seq_Data, VideoParam[SEQ_OFFSET + Index] );
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}
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// Set CRT Controller
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// out 3D4, 0x11, 00 (bit 7 must be 0 to unprotect CRT R0-R7)
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// UnLockCR0_7();
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WRITE_WD_UCHAR( WD_3D4_Index, VERTICAL_RETRACE_END );
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DataByte = READ_WD_UCHAR( WD_3D5_Data );
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DataByte = DataByte & 0x7f;
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WRITE_WD_UCHAR( WD_3D5_Data, DataByte );
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// CRTC controller CR0 - CR18
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for( Index = 0; Index < 25; Index++ )
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{
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WRITE_WD_UCHAR( WD_3D4_Index, Index );
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WRITE_WD_UCHAR( WD_3D5_Data, VideoParam[CRT_OFFSET + Index] );
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}
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// attribute write
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// program palettes and mode register
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for( Index = 0; Index < 21; Index++ )
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{
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WaitForVSync();
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DataByte = READ_WD_UCHAR( Stat1_In ); // Initialize Attr. F/F
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WRITE_WD_UCHAR( Attr_Index, Index );
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// KeStallExecutionProcessor( 5 );
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WRITE_WD_UCHAR( Attr_Data, VideoParam[ATTR_OFFSET + Index] );
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// KeStallExecutionProcessor( 5 );
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WRITE_WD_UCHAR( Attr_Index, 0x20 ); // Set into normal operation
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}
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WRITE_WD_UCHAR( Seq_Index, RESET ); // reset to normal operation !
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WRITE_WD_UCHAR( Seq_Data, 0x03 );
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// graphics controller
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for( Index = 0; Index < 9; Index++ )
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{
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WRITE_WD_UCHAR( GC_Index, Index );
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WRITE_WD_UCHAR( GC_Data, VideoParam[GRAPH_OFFSET + Index] );
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}
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// turn off the text mode cursor
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WRITE_WD_UCHAR( WD_3D4_Index, CURSOR_START );
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WRITE_WD_UCHAR( WD_3D5_Data, 0x2D );
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// Load character fonts into plane 2 (A0000-AFFFF)
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WRITE_WD_UCHAR( Seq_Index, 0x02 ); // Enable Write Plane reg
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WRITE_WD_UCHAR( Seq_Data, 0x04 ); // select plane 2
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WRITE_WD_UCHAR( Seq_Index, 0x04 ); // Memory Mode Control reg
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WRITE_WD_UCHAR( Seq_Data, 0x06 ); // access to all planes,
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WRITE_WD_UCHAR( GC_Index, 0x05 ); // Graphic, Control Mode reg
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WRITE_WD_UCHAR( GC_Data, 0x00 );
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WRITE_WD_UCHAR( GC_Index, 0x06 );
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WRITE_WD_UCHAR( GC_Data, 0x04 );
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WRITE_WD_UCHAR( GC_Index, 0x04 );
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WRITE_WD_UCHAR( GC_Data, 0x02 );
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MemBase = 0xA0000; // Font Plane 2
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for( i = 0; i < 256; i++ )
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{
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for( j = 0; j < 16; j++ )
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{
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WRITE_WD_VRAM( MemBase, VGAFont8x16[i * 16 + j] );
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MemBase++;
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}
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// 32 bytes each character font
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for( j = 16; j < 32; j++ )
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{
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WRITE_WD_VRAM( MemBase, 0 );
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MemBase++;
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}
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}
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// turn on screen
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WRITE_WD_UCHAR( Seq_Index, 0x01 );
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DataByte = READ_WD_UCHAR( Seq_Data );
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DataByte &= 0xdf;
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DataByte ^= 0x0;
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WRITE_WD_UCHAR( Seq_Data, DataByte );
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WaitForVSync();
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// Enable all the planes through the DAC
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WRITE_WD_UCHAR( DAC_Mask, 0xff );
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for( i = 0; i < 768; i++ )
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{
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WRITE_WD_UCHAR( DAC_Data, ColorPalette[i] );
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}
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//
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//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// select plane 0, 1
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WRITE_WD_UCHAR( Seq_Index, 0x02); // Enable Write Plane reg
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WRITE_WD_UCHAR( Seq_Data, VideoParam[SEQ_OFFSET + 0x02] );
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// access to planes 0, 1.
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WRITE_WD_UCHAR( Seq_Index, 0x04); // Memory Mode Control reg
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WRITE_WD_UCHAR( Seq_Data, VideoParam[SEQ_OFFSET+0x04]);
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WRITE_WD_UCHAR( GC_Index, 0x05 ); // Graphic, Control Mode reg
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WRITE_WD_UCHAR( GC_Data, VideoParam[GRAPH_OFFSET + 0x05] );
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WRITE_WD_UCHAR( GC_Index, 0x04);
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WRITE_WD_UCHAR( GC_Data, VideoParam[GRAPH_OFFSET + 0x04] );
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WRITE_WD_UCHAR( GC_Index, 0x06);
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WRITE_WD_UCHAR( GC_Data, VideoParam[GRAPH_OFFSET + 0x06] );
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//
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// Set screen into blue
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//
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for( DataLong = 0xB8000; DataLong < 0xB8FA0; DataLong += 2 )
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{
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WRITE_WD_VRAM( DataLong, 0x20 );
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#ifdef USE_VGA_PALETTE
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WRITE_WD_VRAM( DataLong + 1, 0x07 );
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#else
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WRITE_WD_VRAM( DataLong + 1, 0x1F );
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#endif
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}
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// End of initialize S3 standard VGA +3 mode
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//
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// Initialize the current display column, row, and ownership values.
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//
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Column = 0;
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Row = 0;
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return;
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} /* end of InitializeWD() */
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VOID
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SetWDVGAConfig (
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VOID
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)
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/*++
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Routine Description:
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Set WDVGA compatible configuration except DAC.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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UCHAR SavePR5, SavePR10, SavePR11, SavePR20, SavePR72, Temp;
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PUCHAR pPRtable;
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LockPR( pr1b, NULL );
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LockPR( pr30, NULL );
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UnlockPR( pr20, NULL );
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UnlockPR( pr10, &SavePR10 );
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UnlockPR( pr11, &SavePR11 );
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// non-ISO monitor setting clock
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WRITE_WD_UCHAR( Seq_Index, CLOCKING_MODE );
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Temp = READ_WD_UCHAR( Seq_Data );
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WRITE_WD_UCHAR( Seq_Data, (Temp | 0x01));
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Temp = READ_WD_UCHAR( MiscOutR );
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WRITE_WD_UCHAR( MiscOutW, (Temp & 0xf3));
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// other clocking chip selects
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UnlockPR( pr72_alt, &SavePR72 );
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WRITE_WD_UCHAR( Seq_Index, pr68 );
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Temp = READ_WD_UCHAR( Seq_Data );
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WRITE_WD_UCHAR( Seq_Data, ((Temp & 0xe7) | 0x08));
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RestorePR( pr72_alt, &SavePR72 );
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RestorePR( pr11, &SavePR11 );
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RestorePR( pr10, &SavePR10 );
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LockPR( pr20, NULL );
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// start of WD90C24A2 both screen mode table
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pPRtable = wd90c24a_both;
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while (*pPRtable != END_PVGA) {
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switch (*pPRtable++) {
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case W_CRTC :
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WRITE_WD_UCHAR( WD_3D4_Index, *pPRtable++ );
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WRITE_WD_UCHAR( WD_3D5_Data, *pPRtable++ );
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break;
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case W_SEQ :
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WRITE_WD_UCHAR( Seq_Index, *pPRtable++ );
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WRITE_WD_UCHAR( Seq_Data, *pPRtable++ );
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break;
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case W_GCR :
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WRITE_WD_UCHAR( GC_Index, *pPRtable++ );
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WRITE_WD_UCHAR( GC_Data, *pPRtable++ );
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break;
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default :
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break;
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}
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}
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// unlock FLAT registers
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UnlockPR( pr1b_ual, NULL );
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WRITE_WD_UCHAR( WD_3D4_Index, pr19 );
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WRITE_WD_UCHAR( WD_3D5_Data, ((pr19_s32 & 0xf3) | pr19_CENTER));
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// lock FLAT registers
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LockPR( pr1b, NULL );
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#ifndef USE_VGA_PALETTE
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// PR1/PR4 setting
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UnlockPR( pr5, &SavePR5 );
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WRITE_WD_UCHAR( GCR_Index, pr1 );
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Temp = READ_WD_UCHAR( GCR_Data );
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WRITE_WD_UCHAR( GCR_Data, (Temp | 0x30));
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WRITE_WD_UCHAR( GCR_Index, pr4 );
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Temp = READ_WD_UCHAR( GCR_Data );
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WRITE_WD_UCHAR( GCR_Data, (Temp | 0x01));
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RestorePR( pr5, &SavePR5 );
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// PR16 setting
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UnlockPR( pr10, &SavePR10 );
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WRITE_WD_UCHAR( WD_3D4_Index, pr16 );
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WRITE_WD_UCHAR( WD_3D5_Data, 0);
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RestorePR( pr10, &SavePR10 );
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// PR34a setting
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UnlockPR( pr20, &SavePR20 );
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WRITE_WD_UCHAR( Seq_Index, pr34a );
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WRITE_WD_UCHAR( Seq_Data, 0x0f);
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RestorePR( pr20, &SavePR20 );
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#endif
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} /* SetWDVGAConfig */
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//
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// Internal functions
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//
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VOID
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LockPR (
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USHORT PRnum,
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PUCHAR pPRval
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)
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{
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USHORT pIndex, pData;
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UCHAR Index, Data;
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switch (PRnum) {
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case pr5:
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pIndex = GC_Index;
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pData = GC_Data;
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Index = pr5;
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Data = pr5_lock;
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break;
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case pr10:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr10;
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Data = pr10_lock;
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break;
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case pr11:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr11;
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Data = pr11_lock;
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break;
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case pr1b:
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// case pr1b_ual:
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// case pr1b_ush:
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// case pr1b_upr:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr1b;
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Data = pr1b_lock;
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break;
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case pr20:
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pIndex = Seq_Index;
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pData = Seq_Data;
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Index = pr20;
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Data = pr20_lock;
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break;
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case pr30:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr30;
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Data = pr30_lock;
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break;
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case pr72_alt:
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pIndex = Seq_Index;
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pData = Seq_Data;
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Index = pr72;
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Data = pr72_lock;
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break;
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default:
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return;
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} /* endswitch */
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WRITE_WD_UCHAR( pIndex, Index );
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if (pPRval!=NULL) {
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*pPRval = READ_WD_UCHAR( pData );
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} /* endif */
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WRITE_WD_UCHAR( pData, Data );
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}
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VOID
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UnlockPR (
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USHORT PRnum,
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PUCHAR pPRval
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)
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{
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USHORT pIndex, pData;
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UCHAR Index, Data;
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switch (PRnum) {
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case pr5:
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pIndex = GC_Index;
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pData = GC_Data;
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Index = pr5;
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Data = pr5_unlock;
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break;
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case pr10:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr10;
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Data = pr10_unlock;
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break;
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case pr11:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr11;
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Data = pr11_unlock;
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break;
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// case pr1b:
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case pr1b_ual:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr1b;
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Data = pr1b_unlock;
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break;
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case pr1b_ush:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr1b;
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Data = pr1b_unlock_shadow;
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break;
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case pr1b_upr:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr1b;
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Data = pr1b_unlock_pr;
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break;
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case pr20:
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pIndex = Seq_Index;
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pData = Seq_Data;
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Index = pr20;
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Data = pr20_unlock;
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break;
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case pr30:
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pIndex = WD_3D4_Index;
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pData = WD_3D5_Data;
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Index = pr30;
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Data = pr30_unlock;
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break;
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case pr72_alt:
|
|
pIndex = Seq_Index;
|
|
pData = Seq_Data;
|
|
Index = pr72;
|
|
Data = pr72_unlock;
|
|
break;
|
|
default:
|
|
return;
|
|
} /* endswitch */
|
|
|
|
WRITE_WD_UCHAR( pIndex, Index );
|
|
if (pPRval!=NULL) {
|
|
*pPRval = READ_WD_UCHAR( pData );
|
|
} /* endif */
|
|
WRITE_WD_UCHAR( pData, Data );
|
|
|
|
}
|
|
|
|
VOID
|
|
RestorePR (
|
|
USHORT PRnum,
|
|
PUCHAR pPRval
|
|
)
|
|
{
|
|
USHORT pIndex, pData;
|
|
UCHAR Index, Data;
|
|
switch (PRnum) {
|
|
case pr5:
|
|
pIndex = GC_Index;
|
|
pData = GC_Data;
|
|
Index = pr5;
|
|
break;
|
|
case pr10:
|
|
pIndex = WD_3D4_Index;
|
|
pData = WD_3D5_Data;
|
|
Index = pr10;
|
|
break;
|
|
case pr11:
|
|
pIndex = WD_3D4_Index;
|
|
pData = WD_3D5_Data;
|
|
Index = pr11;
|
|
break;
|
|
case pr1b:
|
|
// case pr1b_ual:
|
|
// case pr1b_ush:
|
|
// case pr1b_upr:
|
|
pIndex = WD_3D4_Index;
|
|
pData = WD_3D5_Data;
|
|
Index = pr1b;
|
|
break;
|
|
case pr20:
|
|
pIndex = Seq_Index;
|
|
pData = Seq_Data;
|
|
Index = pr20;
|
|
break;
|
|
case pr30:
|
|
pIndex = WD_3D4_Index;
|
|
pData = WD_3D5_Data;
|
|
Index = pr30;
|
|
break;
|
|
case pr72_alt:
|
|
pIndex = Seq_Index;
|
|
pData = Seq_Data;
|
|
Index = pr72;
|
|
break;
|
|
default:
|
|
return;
|
|
} /* endswitch */
|
|
|
|
Data = *pPRval;
|
|
WRITE_WD_UCHAR( pIndex, Index );
|
|
WRITE_WD_UCHAR( pData, Data );
|
|
|
|
}
|
|
|
|
|
|
BOOLEAN
|
|
WDIsPresent (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine returns TRUE if an WDVGA is present. It assumes that it's
|
|
already been established that a VGA is present. It performs the Western
|
|
Digital recommended ID test. If all this works, then this is indeed an
|
|
chip from Western Digital.
|
|
|
|
All the registers will be preserved either this function fails to find a
|
|
WD vga or a WD vga is found.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
TRUE if a WDVGA is present, FALSE if not.
|
|
|
|
--*/
|
|
|
|
{
|
|
UCHAR GraphSave0c;
|
|
UCHAR GraphSave0f;
|
|
UCHAR temp1,temp2;
|
|
BOOLEAN status = TRUE;
|
|
|
|
//
|
|
// write 3ce.0c
|
|
//
|
|
|
|
WRITE_WD_UCHAR( GC_Index, pr2 );
|
|
GraphSave0c = temp1 = READ_WD_UCHAR( GC_Data );
|
|
temp1 &= 0xbf;
|
|
WRITE_WD_UCHAR( GC_Data, temp1 );
|
|
|
|
//
|
|
// check 3ce.09 after lock
|
|
//
|
|
|
|
LockPR( pr5, &GraphSave0f ); // lock it
|
|
// WRITE_WD_UCHAR( GC_Index, pr5 );
|
|
// GraphSave0f = READ_WD_UCHAR( GC_Data );
|
|
// WRITE_WD_UCHAR( GC_Data, pr5_lock ); // lock it
|
|
|
|
WRITE_WD_UCHAR( GC_Index, pr0a );
|
|
temp1 = READ_WD_UCHAR( GC_Data );
|
|
WRITE_WD_UCHAR( GC_Data, (UCHAR)(temp1+1) );
|
|
temp2 = READ_WD_UCHAR( GC_Data );
|
|
WRITE_WD_UCHAR( GC_Data, temp1 );
|
|
|
|
if ((temp1+1) == temp2) {
|
|
status = FALSE;
|
|
goto NOT_WDVGA; // locked but writable
|
|
}
|
|
|
|
//
|
|
// check 3ce.09 after unlock
|
|
//
|
|
|
|
UnlockPR( pr5, NULL ); // lock it
|
|
// WRITE_WD_USHORT( GC_Index, (pr5_unlock*0x100+pr5) ); // unlock
|
|
|
|
WRITE_WD_UCHAR( GC_Index, pr0a );
|
|
temp1 = READ_WD_UCHAR( GC_Data );
|
|
WRITE_WD_UCHAR( GC_Data, (UCHAR)(temp1+1) );
|
|
temp2 = READ_WD_UCHAR( GC_Data );
|
|
WRITE_WD_UCHAR( GC_Data, temp1 );
|
|
|
|
if ((temp1+1) != temp2) {
|
|
status = FALSE;
|
|
goto NOT_WDVGA; // unlocked but not-writable
|
|
}
|
|
|
|
NOT_WDVGA:
|
|
|
|
//
|
|
// write 3ce.0c (post-process)
|
|
//
|
|
|
|
WRITE_WD_UCHAR( GC_Index, pr2 );
|
|
WRITE_WD_UCHAR( GC_Data, GraphSave0c);
|
|
|
|
RestorePR( pr5, &GraphSave0f );
|
|
// WRITE_WD_UCHAR( GC_Index, pr5 );
|
|
// WRITE_WD_UCHAR( GC_Data, GraphSave0f);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
/*****************************************************************************/
|