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262 lines
7.2 KiB
262 lines
7.2 KiB
/*++
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Copyright (c) 1994 FirePower Systems, Inc.
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Module Name:
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psidcc.h
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Abstract:
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This header file contains PSI's Display register definitions.
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This includes DCC registers and BT445 registers.
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This header also includes type definitions for values to set
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display modes.
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Author:
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Neil Ogura (9-7-1994)
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Environment:
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Version history:
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--*/
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/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: psidcc.h $
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* $Revision: 1.1 $
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* $Date: 1996/03/08 01:14:14 $
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* $Locker: $
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*/
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//
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// Define DCC register offset
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//
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#define DCC_INDEX_REGISTER_OFFSET 0
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#define DCC_DATA_REGISTER_OFFSET 1
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//
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// Define DCC index values (to be set to DCC INDEX REGISTER)
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//
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#define DCC_ID_INDEX 0x00
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#define DCC_MONITOR_ID_INDEX 0x01
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#define DCC_GPIO_A_INDEX 0x02
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#define DCC_INTERRUPT_STATUS_INDEX 0x03
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#define DCC_PLL_INTERFACE_INDEX 0x04
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#define DCC_TIMING_A_INDEX 0x05
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#define DCC_CONFIG_A_INDEX 0x06
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#define DCC_CONFIG_B_INDEX 0x07
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#define DCC_HORIZ_COUNT_L_INDEX 0x08
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#define DCC_HORIZ_COUNT_H_INDEX 0x09
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#define DCC_VERT_COUNT_L_INDEX 0x0a
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#define DCC_VERT_COUNT_H_INDEX 0x0b
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#define DCC_HORIZ_SYNC_STOP_INDEX 0x0c
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#define DCC_HORIZ_BLANK_STOP_L_INDEX 0x0d
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#define DCC_HORIZ_BLANK_STOP_H_INDEX 0x0e
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#define DCC_HORIZ_DATA_STOP_L_INDEX 0x0f
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#define DCC_HORIZ_DATA_STOP_H_INDEX 0x10
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#define DCC_VERT_SYNC_STOP_INDEX 0x11
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#define DCC_VERT_BLANK_STOP_INDEX 0x12
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#define DCC_VERT_DATA_STOP_L_INDEX 0x13
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#define DCC_VERT_DATA_STOP_H_INDEX 0x14
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#define DCC_COMPO_SYNC_START_L_INDEX 0x15
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#define DCC_COMPO_SYNC_START_H_INDEX 0x16
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#define DCC_LINE_START_INDEX 0x17
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#define DCC_LINE_STOP_INDEX 0x18
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#define DCC_FRAME_START_INDEX 0x19
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#define DCC_FRAME_STOP_INDEX 0x1a
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#define DCC_INTERRUPT_TRIGGER_L_INDEX 0x1b
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#define DCC_INTERRUPT_TRIGGER_H_INDEX 0x1c
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#define DCC_TIMING_B_INDEX 0x1d
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#define DCC_GPIO_B_INDEX 0x1e
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//
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// Define DCC Interrupt Control Values
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//
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#define DCC_INTERRUPT_DETECTED 0x01
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#define DCC_INTERRUPT_CLEAR_AND_DISABLE 0x00
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#define DCC_INTERRUPT_CLEAR_AND_ENABLE 0x02
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//
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// Define DCC GPIO BITS
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//
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#define DCC_GPIO_B_MASK 0xdd
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#define DCC_GPIO_B_1MB_VRAM_MODE 0x20
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#define DCC_GPIO_B_2MB_VRAM_MODE 0x22
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//
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// Define Bt445 register offset
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//
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#define BT445_ADDRESS_REG_OFFSET 0
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#define BT445_PRIMARY_CLUT_REG_OFFSET 1
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#define BT445_GROUP0_REG_OFFSET 2
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#define BT445_OVLAY_CLUT_REG_OFFSET 3
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#define BT445_CONFIG_REG_OFFSET 5
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#define BT445_GROUP1_REG_OFFSET 6
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#define BT445_CURSOR_COLOR_REG_OFFSET 7
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//
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// Bt445 GROUP0 index values (to be set to BT445_ADDRESS_REGISTER
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// before accessing BT445_GROUP0_REGISTER)
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//
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#define BT445_GROUP0_ID_INDEX 0x00
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#define BT445_GROUP0_REVISION_INDEX 0x01
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#define BT445_GROUP0_READ_ENABLE_INDEX 0x04
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#define BT445_GROUP0_BLINK_ENABLE_INDEX 0x05
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#define BT445_GROUP0_COMMAND_INDEX 0x06
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#define BT445_GROUP0_COMMAND_MASK 0x7f
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#define BT445_GROUP0_TEST_INDEX 0x07
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//
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// Bt445 CONFIG index values (to be set to BT445_ADDRESS_REGISTER
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// before accessing BT445_CONFIG_REGISTER)
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//
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#define BT445_CONFIG_RED_POS_INDEX 0x00
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#define BT445_CONFIG_RED_WIDTH_INDEX 0x01
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#define BT445_CONFIG_RED_ENABLE_INDEX 0x02
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#define BT445_CONFIG_RED_BLINK_INDEX 0x03
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#define BT445_CONFIG_GREEN_POS_INDEX 0x08
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#define BT445_CONFIG_GREEN_WIDTH_INDEX 0x09
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#define BT445_CONFIG_GREEN_ENABLE_INDEX 0x0a
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#define BT445_CONFIG_GREEN_BLINK_INDEX 0x0b
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#define BT445_CONFIG_BLUE_POS_INDEX 0x10
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#define BT445_CONFIG_BLUE_WIDTH_INDEX 0x11
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#define BT445_CONFIG_BLUE_ENABLE_INDEX 0x12
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#define BT445_CONFIG_BLUE_BLINK_INDEX 0x13
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#define BT445_CONFIG_OVLAY_POS_INDEX 0x18
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#define BT445_CONFIG_OVLAY_WIDTH_INDEX 0x19
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#define BT445_CONFIG_OVLAY_ENABLE_INDEX 0x1a
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#define BT445_CONFIG_OVLAY_ENABLE_MASK 0x0f
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#define BT445_CONFIG_OVLAY_BLINK_INDEX 0x1b
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#define BT445_CONFIG_OVLAY_BLINK_MASK 0x0f
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#define BT445_CONFIG_CSR_POS_INDEX 0x20
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#define BT445_CONFIG_CSR_WIDTH_INDEX 0x21
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#define BT445_CONFIG_CSR_ENABLE_INDEX 0x22
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#define BT445_CONFIG_CSR_ENABLE_MASK 0x03
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#define BT445_CONFIG_CSR_BLINK_INDEX 0x23
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#define BT445_CONFIG_CSR_BLINK_MASK 0x03
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//
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// Bt445 GROUP1 index values (to be set to BT445_ADDRESS_REGISTER
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// before accessing BT445_GROUP1_REGISTER)
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//
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#define BT445_GROUP1_TEST_INDEX 0x00
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#define BT445_GROUP1_COMMAND_INDEX 0x01
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#define BT445_GROUP1_COMMAND_MASK 0xdf
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#define BT445_GROUP1_DOUT_CTRL_INDEX 0x02
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#define BT445_GROUP1_DOUT_CTRL_MASK 0xbf
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#define BT445_GROUP1_VIDCLK_INDEX 0x03
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#define BT445_GROUP1_VIDCLK_MASK 0x3f
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#define BT445_GROUP1_PLL_RATE_0_INDEX 0x05
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#define BT445_GROUP1_PLL_RATE_0_MASK 0x3f
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#define BT445_GROUP1_PLL_RATE_1_INDEX 0x06
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#define BT445_GROUP1_PLL_RATE_1_MASK 0xcf
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#define BT445_GROUP1_PLL_CTRL_INDEX 0x07
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#define BT445_GROUP1_LOAD_CTRL_INDEX 0x08
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#define BT445_GROUP1_LOAD_CTRL_MASK 0x1c
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#define BT445_GROUP1_START_POS_INDEX 0x09
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#define BT445_GROUP1_FMT_CTRL_INDEX 0x0a
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#define BT445_GROUP1_FMT_CTRL_MASK 0xbb
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#define BT445_GROUP1_MPX_RATE_INDEX 0x0b
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#define BT445_GROUP1_MPX_RATE_MASK 0x3f
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#define BT445_GROUP1_SIGNATURE_INDEX 0x0c
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#define BT445_GROUP1_DEPTH_CTRL_INDEX 0x0d
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#define BT445_GROUP1_LUT_BYPS_POS_INDEX 0x0e
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#define BT445_GROUP1_LUT_BYPS_WID_INDEX 0x0f
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//
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// Bt445 CURSOR_COLOR index values (to be set to BT445_ADDRESS_REGISTER
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// before accessing BT445_CURSOR_COLOR_REGISTER)
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//
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#define BT445_CURSOR_COLOR_0_INDEX 0x00
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#define BT445_CURSOR_COLOR_1_INDEX 0x01
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#define BT445_CURSOR_COLOR_2_INDEX 0x02
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#define BT445_CURSOR_COLOR_3_INDEX 0x03
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//
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// Bt445 ID value
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//
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#define BT445_ID 0x3a
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//
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// Define structures for initializing DCC parameters
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// Fixed portion -- don't change depending on the mode
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//
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typedef struct _DCC_FIXED_REG_INIT {
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UCHAR Interrupt;
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UCHAR ConfigA;
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UCHAR ConfigB_Pre;
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UCHAR ConfigB_Post;
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} DCC_FIXED_REG_INIT,*PDCC_FIXED_REG_INIT;
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//
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// Define structures for initializing DCC parameters
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// Value depends on resolution, pixel depth & freqency
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//
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typedef struct _DCC_REG_INIT {
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UCHAR TimingA;
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UCHAR HorizSyncStop;
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UCHAR VertSyncStop;
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UCHAR VertBlankStop;
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USHORT HorizCount;
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USHORT VertCount;
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USHORT HorizBlankStop;
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USHORT HorizDataStop;
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USHORT VertDataStop;
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USHORT InterruptTrigger;
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} DCC_REG_INIT,*PDCC_REG_INIT;
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//
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// Define structures for initializing Bt445 parameters
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// Fixed portion -- don't change depending on the mode
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//
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typedef struct _BT_FIXED_REG_INIT {
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UCHAR Gr0_ReadEnable;
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UCHAR Gr0_BlinkEnable;
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UCHAR Gr0_Command;
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UCHAR CFG_OvlayPos;
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UCHAR CFG_OvlayWidth;
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UCHAR CFG_OvlayEnable;
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UCHAR CFG_OvlayBlink;
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UCHAR CFG_CursorPos;
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UCHAR CFG_CursorWidth;
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UCHAR CFG_CursorEnable;
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UCHAR CFG_CursorBlink;
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UCHAR Gr1_Command;
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UCHAR Gr1_DoutCtrl;
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UCHAR Gr1_LoadCtrl;
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UCHAR Gr1_LutBypsPos;
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UCHAR Gr1_LutBypsWidth;
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} BT_FIXED_REG_INIT, *PBT_FIXED_REG_INIT;
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//
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// Define structures for initializing Bt445 parameters
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// Variable portion 1 -- depending on VRAM width & pixel width
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//
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typedef struct _BT_REG1_INIT {
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UCHAR CFG_RedPos;
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UCHAR CFG_RedWidth;
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UCHAR CFG_GreenPos;
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UCHAR CFG_GreenWidth;
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UCHAR CFG_BluePos;
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UCHAR CFG_BlueWidth;
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UCHAR Gr1_VidClk;
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UCHAR Gr1_MPXRate;
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UCHAR Gr1_DepthCtrl;
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UCHAR Gr1_StartPos;
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UCHAR Gr1_FmtCtrl;
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} BT_REG1_INIT, *PBT_REG1_INIT;
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//
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// Define structures for initializing Bt445 parameters
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// Variable portion 2 -- depending on resolution, pixel depth & freqency
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//
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typedef struct _BT_REG2_INIT {
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UCHAR Gr1_PllRate0;
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UCHAR Gr1_PllRate1;
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UCHAR Gr1_PllCtrl;
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} BT_REG2_INIT, *PBT_REG2_INIT;
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