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1082 lines
26 KiB
1082 lines
26 KiB
/***********************************************************************
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* Microsoft Puma
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*
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* Microsoft Confidential. Copyright 1994-1996 Microsoft Corporation.
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*
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* Component:
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*
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* File: axp.h
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*
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* File Comments:
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*
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*
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***********************************************************************/
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class ostream;
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struct _IMAGE_RUNTIME_FUNCTION_ENTRY;
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enum TRMTAXP
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{
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trmtaxpUnknown,
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trmtaxpFallThrough,
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trmtaxpBra,
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trmtaxpBraInd,
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trmtaxpBraCc,
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trmtaxpCall,
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trmtaxpCallInd,
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trmtaxpTrapCc,
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};
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// Type (1) Memory Instruction Format.
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// Type (2) Memory Special Instruction Format.
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//
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// 3 2 2 2 2 1 1
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// 1 6 5 1 0 6 5 0
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// +-----------+---------+---------+-------------------------------+
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// | opcode | Ra | Rb | Memory_disp |
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// +-----------+---------+---------+-------------------------------+
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//
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// LDAx Ra.wq,disp.ab(Rb.ab) x = (,H)
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// LDx Ra.wq,disp.ab(Rb.ab) x = (L,Q,F,G,S,T)
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// LDQ_U Ra.wq,disp.ab(Rb.ab)
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// LDx_L Ra.wq,disp.ab(Rb.ab) x = (L,Q)
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// STx_C Ra.mq,disp.ab(Rb.ab) x = (L,Q)
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// STx Ra.rq,disp.ab(Rb.ab) x = (L,Q,F,G,S,T)
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// STQ_U Ra.rq,disp.ab(Rb.ab)
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struct Alpha_Memory_Format
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{
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DWORD MemDisp : 16;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (3) Memory Format Jump Instructions.
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//
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// 3 2 2 2 2 1 1 1 1
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// 1 6 5 1 0 6 5 4 3 0
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// +-----------+---------+---------+---+---------------------------+
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// | opcode | Ra | Rb |Fnc| Hint |
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// +-----------+---------+---------+---+---------------------------+
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//
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// xxx Ra.wq,(Rb.ab),hint xxx = (JMP, JSR, RET, JSR_COROUTINE)
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struct Alpha_Jump_Format
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{
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DWORD Hint : 14;
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DWORD Function : 2;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (4) Branch Instruction Format.
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//
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// 3 2 2 2 2
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// 1 6 5 1 0 0
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// +-----------+---------+-----------------------------------------+
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// | opcode | Ra | Branch_disp |
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// +-----------+---------+-----------------------------------------+
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//
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// Bxx Ra.rq,disp.al x = (EQ,NE,LT,LE,GT,GE,LBC,LBS)
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// BxR Ra.wq,disp.al x = (,S)
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// FBxx Ra.rq,disp.al x = (EQ,NE,LT,LE,GT,GE)
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struct Alpha_Branch_Format
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{
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DWORD BranchDisp : 21;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (5) Operate Register Instruction Format.
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// Type (6) Operate Literal Instruction Format.
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// bop = Rb.rq or #b.ib
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//
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// 3 2 2 2 2 1 1 1 1 1
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// 1 6 5 1 0 6 5 3 2 1 5 4 0
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// +-----------+---------+---------+-----+-+-------------+---------+
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// | opcode | Ra | Rb | SBZ |0| function | Rc |
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// +-----------+---------+---------+-----+-+-------------+---------+
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// 3 2 2 2 2 1 1 1
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// 1 6 5 1 0 3 2 1 5 4 0
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// +-----------+---------+---------------+-+-------------+---------+
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// | opcode | Ra | LIT |1| function | Rc |
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// +-----------+---------+---------------+-+-------------+---------+
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//
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// ADDx Ra.rq,bop,Rc.wq /V x = (Q,L)
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// SxADDy Ra.rq,bop,Rc.wq x = (4,8), y = (Q, L)
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// CMPx Ra.rq,bop,Rc.wq x = (EQ,LT,LE,ULT,ULE)
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// MULx Ra.rq,bop,Rc.wq /V x = (Q,L)
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// UMULH Ra.rq,bop,Rc.wq
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// SUBx Ra.rq,bop,Rc.wq /V x = (Q,L)
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// SxSUBy Ra.rq,bop,Rc.wq x = (4,8), y = (Q, L)
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// xxx Ra.rq,bop,Rc.wq xxx = (AND,BIS,XOR,BIC,ORNOT,EQV)
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// CMOVxx Ra.rq,bop,Rc.wq xx = (EQ,NE,LT,LE,GT,GE,LBC,LBS)
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// SxL Ra.rq,bop,Rc.wq x = (L,R)
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// SRA Ra.rq,bop,Rc.wq
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// CMPBGE Ra.rq,bop,Rc.wq
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// EXTxx Ra.rq,bop,Rc.wq xx = (BL,WL,WH,LL,LH,WL,QH)
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// INSxx Ra.rq,bop,Rc.wq xx = (BL,WL,WH,LL,LH,WL,QH)
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// MSKxx Ra.rq,bop,Rc.wq xx = (BL,WL,WH,LL,LH,WL,QH)
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// ZAPx Ra.rq,bop,Rc.wq x = (,NOT)
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struct Alpha_OpReg_Format
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{
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DWORD Rc : 5;
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DWORD Function : 7;
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DWORD RbvType : 1; // 0 for register format
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DWORD SBZ : 3;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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struct Alpha_OpLit_Format
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{
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DWORD Rc : 5;
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DWORD Function : 7;
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DWORD RbvType : 1; // 1 for literal format
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DWORD Literal : 8;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (7) Floating-point Operate Instruction Format.
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// Type (8) Floating-point Convert Instruction Format.
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//
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// Type 6 and 7 are the same, except for type 7
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// Fc == F31 (1s) and Fb is the source.
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//
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// 3 2 2 2 2 1 1
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// 1 6 5 1 0 6 5 5 4 0
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// +-----------+---------+---------+---------------------+---------+
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// | opcode | Fa | Fb | function | Fc |
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// +-----------+---------+---------+---------------------+---------+
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struct Alpha_FpOp_Format
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{
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DWORD Fc : 5;
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DWORD Function : 11;
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DWORD Fb : 5;
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DWORD Fa : 5;
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DWORD Opcode : 6;
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};
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// Type (9) PALcode Instruction Format.
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//
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// 3 2 2
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// 1 6 5 0
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// +-----------+---------------------------------------------------+
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// | opcode | PALcode func |
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// +-----------+---------------------------------------------------+
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struct Alpha_PAL_Format
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{
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DWORD Function : 26;
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DWORD Opcode : 6;
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};
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// Type (10) EV4 MTPR/MFPR PAL mode instructions.
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//
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// 3 2 2 2 2 1 1
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// 1 6 5 1 0 6 5 8 7 6 5 4 0
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// +-----------+---------+---------+---------------+-+-+-+---------+
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// | opcode | Ra | Rb | IGN |P|A|I| Index |
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// +-----------+---------+---------+---------------+-+-+-+---------+
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struct Alpha_EV4_PR_Format
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{
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DWORD Index : 5;
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DWORD Ibox : 1;
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DWORD Abox : 1;
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DWORD PalTemp : 1;
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DWORD IGN : 8;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (10) EV5 MTPR/MFPR PAL mode instructions.
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//
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// 3 2 2 2 2 1 1
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// 1 6 5 1 0 6 5 0
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// +-----------+---------+---------+-------------------------------+
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// | opcode | Ra | Rb | Index |
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// +-----------+---------+---------+-------------------------------+
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struct Alpha_EV5_PR_Format
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{
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DWORD Index : 16;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (11) EV4 special memory PAL mode access.
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//
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// 3 2 2 2 2 1 1 1 1 1 1
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// 1 6 5 1 0 6 5 4 3 2 1 0
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// +-----------+---------+---------+-+-+-+-+-----------------------+
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// | opcode | Ra | Rb |P|A|R|Q| Disp |
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// +-----------+---------+---------+-+-+-+-+-----------------------+
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struct Alpha_EV4_MEM_Format
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{
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DWORD Disp : 12;
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DWORD QuadWord : 1;
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DWORD RWcheck : 1;
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DWORD Alt : 1;
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DWORD Physical : 1;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (11) EV5 special memory PAL mode access.
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//
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// 3 2 2 2 2 1 1 1 1 1 1
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// 1 6 5 1 0 6 5 4 3 2 1 0
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// +-----------+---------+---------+-+-+-+-+-----------------------+
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// | opcode | Ra | Rb |P|A|R|Q| Disp |
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// +-----------+---------+---------+-+-+-+-+-----------------------+
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struct Alpha_EV5_MEM_Format
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{
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DWORD Disp : 10;
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DWORD Lock_Cond: 1;
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DWORD Vpte: 1;
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DWORD QuadWord : 1;
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DWORD RWcheck : 1;
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DWORD Alt : 1;
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DWORD Physical : 1;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (12) EV4 PAL mode switch.
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//
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// 3 2 2 2 2 1 1 1 1
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// 1 6 5 1 0 6 5 4 3 0
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// +-----------+---------+---------+-+-+---------------------------+
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// | opcode | Ra | Rb |1|0| IGN |
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// +-----------+---------+---------+-+-+---------------------------+
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struct Alpha_EV4_REI_Format
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{
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DWORD IGN : 14;
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DWORD zero : 1;
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DWORD one : 1;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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// Type (12) EV5 PAL mode switch.
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//
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// 3 2 2 2 2 1 1 1 1
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// 1 6 5 1 0 6 5 4 3 0
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// +-----------+---------+---------+-+-+---------------------------+
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// | opcode | Ra | Rb |1|0| IGN |
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// +-----------+---------+---------+-+-+---------------------------+
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struct Alpha_EV5_REI_Format
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{
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DWORD IGN : 14;
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DWORD Type: 2;
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DWORD Rb : 5;
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DWORD Ra : 5;
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DWORD Opcode : 6;
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};
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union AXPIW // AXP Instruction Word
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{
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DWORD dw;
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Alpha_Memory_Format Memory;
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Alpha_Jump_Format Jump;
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Alpha_Branch_Format Branch;
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Alpha_OpReg_Format OpReg;
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Alpha_OpLit_Format OpLit;
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Alpha_FpOp_Format FpOp;
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Alpha_PAL_Format Pal;
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Alpha_EV4_PR_Format EV4_PR;
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Alpha_EV5_PR_Format EV5_PR;
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Alpha_EV4_MEM_Format EV4_MEM;
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Alpha_EV5_MEM_Format EV5_MEM;
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Alpha_EV4_REI_Format EV4_REI;
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Alpha_EV5_REI_Format EV5_REI;
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};
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class DISAXP : public DIS
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{
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public:
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DISAXP(ARCHT);
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enum REG
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{
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regR0 = 0,
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regR1 = 1,
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regR2 = 2,
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regR3 = 3,
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regR4 = 4,
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regR5 = 5,
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regR6 = 6,
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regR7 = 7,
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regR8 = 8,
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regR9 = 9,
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regR10 = 10,
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regR11 = 11,
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regR12 = 12,
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regR13 = 13,
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regR14 = 14,
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regR15 = 15,
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regR16 = 16,
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regR17 = 17,
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regR18 = 18,
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regR19 = 19,
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regR20 = 20,
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regR21 = 21,
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regR22 = 22,
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regR23 = 23,
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regR24 = 24,
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regR25 = 25,
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regR26 = 26,
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regR27 = 27,
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regR28 = 28,
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regR29 = 29,
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regR30 = 30,
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regR31 = 31,
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regV0 = 0,
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regT0 = 1,
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regT1 = 2,
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regT2 = 3,
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regT3 = 4,
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regT4 = 5,
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regT5 = 6,
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regT6 = 7,
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regT7 = 8,
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regS0 = 9,
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regS1 = 10,
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regS2 = 11,
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regS3 = 12,
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regS4 = 13,
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regS5 = 14,
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regFp = 15,
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regA0 = 16,
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regA1 = 17,
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regA2 = 18,
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regA3 = 19,
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regA4 = 20,
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regA5 = 21,
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regT8 = 22,
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regT9 = 23,
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regT10 = 24,
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regT11 = 25,
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regRa = 26,
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regT12 = 27,
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regAt = 28,
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regGp = 29,
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regSp = 30,
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regZero = 31,
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regF0 = 32,
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regF1 = 33,
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regF2 = 34,
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regF3 = 35,
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regF4 = 36,
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regF5 = 37,
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regF6 = 38,
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regF7 = 39,
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regF8 = 40,
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regF9 = 41,
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regF10 = 42,
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regF11 = 43,
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regF12 = 44,
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regF13 = 45,
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regF14 = 46,
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regF15 = 47,
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regF16 = 48,
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regF17 = 49,
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regF18 = 50,
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regF19 = 51,
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regF20 = 52,
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regF21 = 53,
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regF22 = 54,
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regF23 = 55,
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regF24 = 56,
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regF25 = 57,
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regF26 = 58,
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regF27 = 59,
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regF28 = 60,
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regF29 = 61,
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regF30 = 62,
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regF31 = 63,
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};
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// Methods inherited from DIS
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ADDR AddrAddress() const;
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ADDR AddrJumpTable() const;
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ADDR AddrOperand(size_t) const;
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ADDR AddrTarget() const;
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size_t Cb() const;
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size_t CbDisassemble(ADDR, const BYTE *, size_t);
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size_t CbGenerateLoadAddress(BYTE *, size_t, size_t * = NULL) const;
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size_t CbJumpEntry() const;
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size_t CbMemoryReference() const;
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size_t CchFormatAddr(ADDR, char *, size_t) const;
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size_t CchFormatBytes(char *, size_t) const;
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size_t CchFormatBytesMax() const;
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size_t CchFormatInstr(char *, size_t) const;
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size_t Coperand() const;
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void FormatAddr(ostream&, ADDR) const;
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void FormatInstr(ostream&) const;
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MEMREFT Memreft() const;
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TRMT Trmt() const;
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TRMTA Trmta() const;
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private:
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enum OPCLS // Operand Class
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{
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opclsNone, // No operand
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opclsRa_w, // General purpose register Ra (write)
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opclsRa_m, // General purpose register Ra (read/write)
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opclsRa_r, // General purpose register Ra (read)
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opclsRb_r, // General purpose register Rb (read)
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opclsRbLb, // General purpose register Rb (read) or literal in Rb field
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opclsRc_w, // General purpose register Rc (write)
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opclsFa_w, // Floating point register Fa (write)
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opclsFa_r, // Floating point register Fa (read)
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opclsFb_r, // Floating point register Fb (read)
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opclsFc_w, // Floating point register Fc (write)
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opclsMem, // Memory reference: disp.ab(Rb.ab)
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opclsMemHigh, // Memory reference: disp.ab(Rb.ab)
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opclsMem_r, // Memory read: disp.ab(Rb.ab)
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opclsMem_w, // Memory write: disp.ab(Rb.ab)
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opclsEv4Mem_r, // Memory read: disp.ab(Rb.ab)
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opclsEv4Mem_w, // Memory write: disp.ab(Rb.ab)
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opclsBra, // Branch instruction target
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opclsJmp, // Jump instruction target: (Rb.ab)
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opclsHint1, // Jump target hint
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opclsHint2, // RET/JSR_COROUTINE hint
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opclsPal, // CALL_PAL instruction operand
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opclsFetch, // FETCH instruction operand
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};
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enum ICLS // Instruction Class
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{
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// Invalid Class
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iclsInvalid,
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// LoadAddr Class
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//
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// Text Format: LDA ra,disp(rb)
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//
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// Termination Type: trmtaxpFallThrough
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//
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// Registers Used: rb
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// Registers Set: ra
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iclsLoadAddr,
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// LoadAddrH Class
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//
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// Text Format: LDAH ra,disp(rb)
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//
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// Termination Type: trmtaxpFallThrough
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//
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// Registers Used: rb
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// Registers Set: ra
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iclsLoadAddrH,
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// Load Class
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//
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// Text Format: LDQ_U ra,disp(rb)
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//
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// Termination Type: trmtaxpFallThrough
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//
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// Registers Used: rb
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// Registers Set: ra
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iclsLoad,
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// Store Class
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//
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// Text Format: STL ra,disp(rb)
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//
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// Termination Type: trmtaxpFallThrough
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//
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// Registers Used: ra, rb
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// Registers Set:
|
|
|
|
iclsStore,
|
|
|
|
// Conditional Store Class
|
|
//
|
|
// Text Format: STL_C ra,disp(rb)
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: ra, rb
|
|
// Registers Set: ra
|
|
|
|
iclsStoreCc,
|
|
|
|
// Call Class
|
|
//
|
|
// Text Format: BSR ra,Target
|
|
//
|
|
// Termination Type: trmtaxpCall
|
|
//
|
|
// Registers Used:
|
|
// Registers Set: ra
|
|
|
|
iclsCall,
|
|
|
|
// Conditional Branch Class
|
|
//
|
|
// Text Format: BEQ ra,Target
|
|
//
|
|
// Termination Type: trmtaxpBraCc
|
|
//
|
|
// Registers Used: ra
|
|
// Registers Set:
|
|
|
|
iclsBraCc,
|
|
|
|
// Jump Class
|
|
//
|
|
// Text Format: JMP ra,(rb),hint
|
|
//
|
|
// Termination Type: trmtaxpBraInd
|
|
//
|
|
// Registers Used: rb
|
|
// Registers Set: ra
|
|
|
|
iclsJmp,
|
|
|
|
// Register Class
|
|
//
|
|
// Text Format: ADDL ra,rb,rc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: ra, rb
|
|
// Registers Set: rc
|
|
|
|
iclsReg,
|
|
|
|
// Register w/Trap Class
|
|
//
|
|
// Text Format: ADDL/V ra,rb,rc
|
|
//
|
|
// Termination Type: trmtaxpTrapCc
|
|
//
|
|
// Registers Used: ra, rb
|
|
// Registers Set: rc
|
|
|
|
iclsRegTrap,
|
|
|
|
// Floating Point Load Class
|
|
//
|
|
// Text Format: LDF fa,disp(rb)
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: rb
|
|
// Registers Set: fa
|
|
|
|
iclsLoadFp,
|
|
|
|
// Floating Point Store Class
|
|
//
|
|
// Text Format: STF fa,disp(rb)
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fa, rb
|
|
// Registers Set:
|
|
|
|
iclsStoreFp,
|
|
|
|
// Floating Point Conditional Branch Class
|
|
//
|
|
// Text Format: FBEQ fa,Target
|
|
//
|
|
// Termination Type: trmtaxpBraCc
|
|
//
|
|
// Registers Used: fa
|
|
// Registers Set:
|
|
|
|
iclsBraCcFp,
|
|
|
|
// Floating Point Register Class
|
|
//
|
|
// Text Format: CPYS fa,fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fa, fb
|
|
// Registers Set: fc
|
|
|
|
iclsRegFp,
|
|
|
|
// Floating Point Register Class
|
|
//
|
|
// Text Format: ADDS fa,fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fa, fb
|
|
// Registers Set: fc
|
|
|
|
iclsRegFp1,
|
|
|
|
// Floating Point Register Class
|
|
//
|
|
// Text Format: CMPDEQ fa,fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fa, fb
|
|
// Registers Set: fc
|
|
|
|
iclsRegFp2,
|
|
|
|
// Floating Point Register Class
|
|
//
|
|
// Text Format: ADDF fa,fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fa, fb
|
|
// Registers Set: fc
|
|
|
|
iclsRegFp5,
|
|
|
|
// Two Operand Floating Point Register Class
|
|
//
|
|
// Text Format: CVTLQ fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fb
|
|
// Registers Set: fc
|
|
//
|
|
// Constraints: fa must be f31
|
|
|
|
iclsReg2Fp,
|
|
|
|
// Two Operand Floating Point Register Class
|
|
//
|
|
// Text Format: CVTLQ fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fb
|
|
// Registers Set: fc
|
|
//
|
|
// Constraints: fa must be f31
|
|
|
|
iclsReg2Fp1,
|
|
|
|
// Two Operand Floating Point Register Class
|
|
//
|
|
// Text Format: CVTLQ fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fb
|
|
// Registers Set: fc
|
|
//
|
|
// Constraints: fa must be f31
|
|
|
|
iclsReg2Fp3,
|
|
|
|
// Two Operand Floating Point Register Class
|
|
//
|
|
// Text Format: CVTLQ fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fb
|
|
// Registers Set: fc
|
|
//
|
|
// Constraints: fa must be f31
|
|
|
|
iclsReg2Fp4,
|
|
|
|
// Two Operand Floating Point Register Class
|
|
//
|
|
// Text Format: CVTLQ fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fb
|
|
// Registers Set: fc
|
|
//
|
|
// Constraints: fa must be f31
|
|
|
|
iclsReg2Fp6,
|
|
|
|
// Two Operand Floating Point Register Class
|
|
//
|
|
// Text Format: CVTLQ fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fb
|
|
// Registers Set: fc
|
|
//
|
|
// Constraints: fa must be f31
|
|
|
|
iclsReg2Fp7,
|
|
|
|
// Two Operand Floating Point Register Class
|
|
//
|
|
// Text Format: CVTQL fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fb
|
|
// Registers Set: fc
|
|
//
|
|
// Constraints: fa must be f31
|
|
|
|
iclsCvtql,
|
|
|
|
// MT_FPCR/MF_FPCR Instruction Class
|
|
//
|
|
// Text Format: MT_FPCR fa,fb,fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: fa, fb, fc
|
|
// Registers Set:
|
|
//
|
|
// Constraints: fa, fb, and fc must be the same
|
|
|
|
iclsFpcr,
|
|
|
|
// CALL_PAL Instruction Class
|
|
//
|
|
// Text Format: CALL_PAL ???
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: ???
|
|
// Registers Set: ???
|
|
|
|
iclsPal,
|
|
|
|
// FETCH/FETCHM Class
|
|
//
|
|
// Text Format: FETCH 0(rb)
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: rb
|
|
// Registers Set:
|
|
|
|
iclsFetch,
|
|
|
|
// No Operand Instruction
|
|
//
|
|
// Text Format: MB
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsNone,
|
|
|
|
// RPCC/RC/RS Instruction Class
|
|
//
|
|
// Text Format: RPCC ra
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set: ra
|
|
|
|
iclsRa_w,
|
|
|
|
// EV4 REI Instruction Class
|
|
//
|
|
// Text Format: HW_REI
|
|
//
|
|
// Termination Type: trmtaxpBraInd
|
|
//
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsEv4Rei,
|
|
|
|
// EV4 PR Instruction Class
|
|
//
|
|
// Text Format: HW_MTPR Ra,Rb
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsEv4Pr,
|
|
|
|
// EV4 Memory Load Class
|
|
//
|
|
// Text Format: HW_LD ra,disp(rb)
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsEv4Load,
|
|
|
|
// EV4 Memory Store Class
|
|
//
|
|
// Text Format: HW_ST ra,disp(rb)
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsEv4Store,
|
|
|
|
// Branch Class
|
|
//
|
|
// Text Format: BR Target
|
|
//
|
|
// Termination Type: trmtaxpBra
|
|
//
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsBra,
|
|
|
|
// One Operand Register Class
|
|
//
|
|
// Text Format: CLR rc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set: rc
|
|
|
|
iclsReg1,
|
|
|
|
// MOV Instruction Class
|
|
//
|
|
// Text Format: MOV lit,ra
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set: ra
|
|
|
|
iclsMov,
|
|
|
|
// Two Operand Register Class
|
|
//
|
|
// Text Format: MOV rb,rc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used: rb
|
|
// Registers Set: rc
|
|
|
|
iclsReg2,
|
|
|
|
// Two Operand Register Class
|
|
//
|
|
// Text Format: NEGL/V rb,rc
|
|
//
|
|
// Termination Type: trmtaxpTrapCc
|
|
//
|
|
// Registers Used: rb
|
|
// Registers Set: rc
|
|
|
|
iclsReg2Trap,
|
|
|
|
// One Operand Register Class
|
|
//
|
|
// Text Format: FCLR fc
|
|
//
|
|
// Termination Type: trmtaxpFallThrough
|
|
//
|
|
// Registers Used:
|
|
// Registers Set: fc
|
|
|
|
iclsReg1Fp,
|
|
|
|
// UNDONE: Add comments
|
|
|
|
iclsRet1,
|
|
iclsRet2,
|
|
iclsRet3,
|
|
iclsRet4,
|
|
iclsRet5,
|
|
iclsRet6,
|
|
iclsRet7,
|
|
iclsRet8,
|
|
};
|
|
|
|
struct CLS
|
|
{
|
|
BYTE trmtaxp;
|
|
BYTE rgopcls[3]; // Operand class for each operand
|
|
};
|
|
|
|
struct OPCD
|
|
{
|
|
const char *szMnemonic;
|
|
BYTE icls;
|
|
};
|
|
|
|
enum PALOP
|
|
{
|
|
// The following PAL operations are privileged
|
|
|
|
palopHalt = 0x00,
|
|
palopRestart = 0x01,
|
|
palopDraina = 0x02,
|
|
palopReboot = 0x03,
|
|
palopInitpal = 0x04,
|
|
palopWrentry = 0x05,
|
|
palopSwpirql = 0x06,
|
|
palopRdirql = 0x07,
|
|
palopDi = 0x08,
|
|
palopEi = 0x09,
|
|
palopSwppal = 0x0A,
|
|
palopSsir = 0x0C,
|
|
palopCsir = 0x0D,
|
|
palopRfe = 0x0E,
|
|
palopRetsys = 0x0F,
|
|
palopSwpctx = 0x10,
|
|
palopSwpprocess = 0x11,
|
|
palopRdmces = 0x12,
|
|
palopWrmces = 0x13,
|
|
palopTbia = 0x14,
|
|
palopTbis = 0x15,
|
|
palopDtbis = 0x16,
|
|
palopTbisasn = 0x17,
|
|
palopRdksp = 0x18,
|
|
palopSwpksp = 0x19,
|
|
palopRdpsr = 0x1A,
|
|
palopRdpcr = 0x1C,
|
|
palopRdthread = 0x1E,
|
|
palopTbim = 0x20,
|
|
palopTbimasn = 0x21,
|
|
palopRdcounters = 0x30,
|
|
palopRdstate = 0x31,
|
|
palopWrperfmon = 0x32,
|
|
palopInitpcr = 0x38, // EV4 (21064) specific
|
|
|
|
// The following PAL operations are unprivileged
|
|
|
|
palopBpt = 0x80,
|
|
palopCallsys = 0x83,
|
|
palopImb = 0x86,
|
|
palopGentrap = 0xAA,
|
|
palopRdteb = 0xAB,
|
|
palopKbpt = 0xAC,
|
|
palopCallkd = 0xAD,
|
|
};
|
|
|
|
struct PALMAP
|
|
{
|
|
PALOP palop;
|
|
const char *szFunction;
|
|
};
|
|
|
|
static const TRMT mptrmtaxptrmt[];
|
|
|
|
static const CLS rgcls[];
|
|
|
|
static const OPCD rgopcd[];
|
|
static const OPCD rgopcdArith[];
|
|
static const OPCD rgopcdBit[];
|
|
static const OPCD rgopcdByte[];
|
|
static const OPCD rgopcdMul[];
|
|
static const OPCD rgopcdVax[];
|
|
static const OPCD rgopcdIEEE[];
|
|
static const OPCD rgopcdFP[];
|
|
static const OPCD rgopcdMemSpc[];
|
|
static const OPCD rgopcdJump[];
|
|
static const OPCD rgopcdSext[];
|
|
|
|
static const OPCD opcdBr_;
|
|
static const OPCD opcdClr;
|
|
static const OPCD opcdFabs;
|
|
static const OPCD opcdFclr;
|
|
static const OPCD opcdFmov;
|
|
static const OPCD opcdFneg;
|
|
static const OPCD opcdFnop;
|
|
static const OPCD opcdMf_Fpcr;
|
|
static const OPCD opcdMov1;
|
|
static const OPCD opcdMov2;
|
|
static const OPCD opcdMt_Fpcr;
|
|
static const OPCD opcdNegf;
|
|
static const OPCD opcdNegg;
|
|
static const OPCD opcdNegl;
|
|
static const OPCD opcdNegl_V;
|
|
static const OPCD opcdNegq;
|
|
static const OPCD opcdNegq_V;
|
|
static const OPCD opcdNegs;
|
|
static const OPCD opcdNegt;
|
|
static const OPCD opcdNop;
|
|
static const OPCD opcdNot;
|
|
static const OPCD opcdSextl;
|
|
|
|
static const DWORD dwValidQualifier1;
|
|
static const DWORD dwValidQualifier2;
|
|
static const DWORD dwValidQualifier3;
|
|
static const DWORD dwValidQualifier4;
|
|
static const DWORD dwValidQualifier5;
|
|
static const DWORD dwValidQualifier6;
|
|
static const DWORD dwValidQualifier7;
|
|
static const DWORD dwValidQualifier8;
|
|
|
|
static const char rgszQualifier1[32][8];
|
|
static const char rgszQualifier2[32][8];
|
|
|
|
static const PALMAP rgpalmap[];
|
|
static const size_t cpalmap;
|
|
|
|
static const char rgszGpr[32][8];
|
|
|
|
void FormatHex(ostream&, DWORD) const;
|
|
void FormatOperand(ostream&, OPCLS opcls) const;
|
|
void FormatRegRel(ostream&, REG, DWORD) const;
|
|
bool FValidOperand(size_t) const;
|
|
static const OPCD *PopcdDecode(AXPIW);
|
|
const OPCD *PopcdPseudoOp(OPCD *, char *) const;
|
|
TRMTAXP Trmtaxp() const;
|
|
|
|
AXPIW m_axpiw;
|
|
const OPCD *m_popcd;
|
|
};
|