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136 lines
3.6 KiB
136 lines
3.6 KiB
/*[
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======================================================================
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SoftPC Revision 3.0
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Title:
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cpu_vid.h
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Description:
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This module supports the interface between the cpu
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and the video emulation code.
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Author:
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John Shanly
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Date:
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12 April 1991
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SccsID @(#)cpu_vid.h 1.11 03/09/94
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(c)Copyright Insignia Solutions Ltd., 1991. All rights reserved.
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======================================================================
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]*/
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typedef struct
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{
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void (*b_write) IPT2(ULONG, value, ULONG, offset);
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void (*w_write) IPT2(ULONG, value, ULONG, offset);
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#ifndef NO_STRING_OPERATIONS
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void (*b_fill) IPT3(ULONG, value, ULONG, offset, ULONG, count);
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void (*w_fill) IPT3(ULONG, value, ULONG, offset, ULONG, count);
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void (*b_fwd_move) IPT4(ULONG, offset, ULONG, eas, ULONG, count,
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ULONG, src_flag);
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void (*b_bwd_move) IPT4(ULONG, offset, ULONG, eas, ULONG, count,
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ULONG, src_flag);
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void (*w_fwd_move) IPT4(ULONG, offset, ULONG, eas, ULONG, count,
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ULONG, src_flag);
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void (*w_bwd_move) IPT4(ULONG, offset, ULONG, eas, ULONG, count,
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ULONG, src_flag);
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#endif /* NO_STRING_OPERATIONS */
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} WRT_POINTERS;
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typedef struct
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{
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void (*b_write) IPT2(IU8, eaOff, IU32, eaVal);
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void (*w_write) IPT2(IU16, eaOff, IU32, eaVal);
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void (*d_write) IPT2(IU32, eaOff, IU32, eaVal);
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void (*b_fill) IPT3(IU32, eaOff, IU8, eaVal, IU32, count);
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void (*w_fill) IPT3(IU32, eaOff, IU16, eaVal, IU32, count);
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void (*d_fill) IPT3(IU32, eaOff, IU32, eaVal, IU32, count);
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void (*b_fwd_move) IPT4(IU32, eaVal, IHPE, fromOff, IU32, count, IBOOL, src_flag);
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void (*b_bwd_move) IPT4(IU32, eaVal, IHPE, fromOff, IU32, count, IBOOL, src_flag);
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void (*w_fwd_move) IPT4(IU32, eaVal, IHPE, fromOff, IU32, count, IBOOL, src_flag);
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void (*w_bwd_move) IPT4(IU32, eaVal, IHPE, fromOff, IU32, count, IBOOL, src_flag);
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void (*d_fwd_move) IPT4(IU32, eaVal, IHPE, fromOff, IU32, count, IBOOL, src_flag);
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void (*d_bwd_move) IPT4(IU32, eaVal, IHPE, fromOff, IU32, count, IBOOL, src_flag);
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} EVID_WRT_POINTERS;
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typedef struct
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{
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WRT_POINTERS mode_0[32];
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WRT_POINTERS mode_1[2];
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WRT_POINTERS mode_2[16];
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#ifdef VGG
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WRT_POINTERS mode_3[16];
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#endif
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} CHN_TABLE;
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typedef struct
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{
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CHN_TABLE nch;
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#ifdef VGG
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CHN_TABLE ch4;
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#endif
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} MODE_TABLE;
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extern MODE_TABLE mode_table;
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typedef struct
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{
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IU32 (*b_read) IPT1(ULONG, offset);
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IU32 (*w_read) IPT1(ULONG, offset);
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#ifndef NO_STRING_OPERATIONS
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void (*str_read) IPT3(IU8 *, dest, ULONG, offset, ULONG, count);
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#endif /* NO_STRING_OPERATIONS */
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} READ_POINTERS;
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typedef struct
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{
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IU32 (*b_read) IPT1(IU32, eaOff);
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IU32 (*w_read) IPT1(IU32, eaOff);
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IU32 (*d_read) IPT1(IU32, eaOff);
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void (*str_fwd_read) IPT3(IU8 *, dest, IU32, eaOff, IU32, count);
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void (*str_bwd_read) IPT3(IU8 *, dest, IU32, eaOff, IU32, count);
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} EVID_READ_POINTERS;
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extern READ_POINTERS read_pointers;
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#ifndef Cpu_set_vid_wrt_ptrs
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extern void Cpu_set_vid_wrt_ptrs IPT1( WRT_POINTERS *, ptrs );
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extern void Cpu_set_vid_rd_ptrs IPT1( READ_POINTERS *, ptrs );
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#endif /* Cpu_set_vid_wrt_ptrs */
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#ifndef CPU_40_STYLE
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#ifdef A3CPU
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#ifdef C_VID
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extern WRT_POINTERS Glue_writes;
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#endif /* C_VID */
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#else /* A3CPU */
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#ifdef C_VID
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extern MEM_HANDLERS Glue_writes;
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#endif /* C_VID */
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#endif /* A3CPU */
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#endif /* CPU_40_STYLE */
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extern WRT_POINTERS simple_writes;
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extern WRT_POINTERS dth_md0_writes, dth_md1_writes, dth_md2_writes, dth_md3_writes;
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extern WRT_POINTERS ch2_md0, ch2_md1, ch2_md2, ch2_md3, ch2_mdcopy;
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extern READ_POINTERS Glue_reads;
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extern READ_POINTERS simple_reads, pointers_RAM_off;
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extern READ_POINTERS pointers_mode0_nch, pointers_mode0_ch4, pointers_mode0_ch2;
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extern READ_POINTERS pointers_mode1_nch, pointers_mode1_ch4, pointers_mode1_ch2;
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