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406 lines
14 KiB
406 lines
14 KiB
/*
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d_oper.h
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Define all Decoded Operand Types.
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*/
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/*
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static char SccsID[]="@(#)d_oper.h 1.1 05 Oct 1993 Copyright Insignia Solutions Ltd.";
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*/
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/*
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The Decoded Intel Operands.
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---------------------------
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The naming convention used is similiar to that used in the Intel
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documentation for the 386 or 486 processors. See Appendix A - The
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Opcode Map, for details.
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Each decoded operand has an argument type, identifiers,
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addressability indication and specific values associated with it.
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The exact return values for each operand are listed below. The values
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should only be accessed through the macros provided, the layout may
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be changed in the future. The macros take a pointer to a DECODED_ARG
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as their argument.
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Operands are encoded in a two letter plus optional size form:-
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<addressing method><operand type><size>
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Addressing methods are denoted by upper case letters, viz:-
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C The operand is a control register.
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register identifier. DCD_IDENTIFIER
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addressability(Read/Write). DCD_ADDRESSABILITY
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D The operand is a debug register.
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register identifier. DCD_IDENTIFIER
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addressability(Read/Write). DCD_ADDRESSABILITY
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I The operand is an immediate value.
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immediate identifier. DCD_IDENTIFIER
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addressability(Read/Write). DCD_ADDRESSABILITY
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the value. DCD_IMMED1
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J The operand is a relative offset.
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addressability(Read/Write). DCD_ADDRESSABILITY
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the value. DCD_IMMED1
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K The operand is two immediate values.
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addressability(Read/Write). DCD_ADDRESSABILITY
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the first value. DCD_IMMED1
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the second value. DCD_IMMED2
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M The operand is held in memory.
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addressing mode. DCD_IDENTIFIER
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sub type of addressing mode. DCD_SUBTYPE
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addressability(Read/Write). DCD_ADDRESSABILITY
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segment register identifier. DCD_SEGMENT_ID
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addressing displacement. DCD_DISP
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R The operand is a general register.
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register identifier. DCD_IDENTIFIER
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addressability(Read/Write). DCD_ADDRESSABILITY
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S The operand is a segment register.
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register identifier. DCD_IDENTIFIER
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addressability(Read/Write). DCD_ADDRESSABILITY
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T The operand is a test register.
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register identifier. DCD_IDENTIFIER
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addressability(Read/Write). DCD_ADDRESSABILITY
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V The operand is a register in the co-processor stack.
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stack addressing mode. DCD_IDENTIFIER
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addressability(Read/Write). DCD_ADDRESSABILITY
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stack relative register identifier. DCD_INDEX
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Operand types are denoted by lower case letters, viz:-
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a operand pair in memory, as used by BOUND.
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<size> = 16 word operands.
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<size> = 32 double word operands.
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b byte.
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d double word.
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i floating point integer
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<size> 16 16-bit word integer
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<size> 32 32-bit short integer
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<size> 64 64-bit long integer
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<size> 80 80-bit packed decimal integer
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p far pointer.
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<size> = 16 16:16 ptr (ie 32-bit)
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<size> = 32 16:32 ptr (ie 48-bit)
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r floating point real
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<size> = 32 32-bit short real
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<size> = 64 64-bit long real
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<size> = 80 80-bit temp real
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w word.
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s six-byte descriptor.
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Additionally the 'M' addressing method has a form with no operand
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type, but the following optional sizes:-
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<size> 14 = 14-byte data block
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<size> 28 = 28-byte data block
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<size> 94 = 94-byte data block
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<size> 108 = 108-byte data block
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*/
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/*
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The argument types:-
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*/
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#define A_ (UTINY) 0
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#define A_Rb (UTINY) 1 /* aka r8,r/m8 */
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#define A_Rw (UTINY) 2 /* aka r16,r/m16 */
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#define A_Rd (UTINY) 3 /* aka r32,r/m32 */
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#define A_Sw (UTINY) 4 /* aka Sreg */
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#define A_Cd (UTINY) 5 /* aka CRx */
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#define A_Dd (UTINY) 6 /* aka DRx */
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#define A_Td (UTINY) 7 /* aka TRx */
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#define A_M (UTINY) 8 /* aka m */
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#define A_M14 (UTINY) 9 /* aka m14byte */
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#define A_M28 (UTINY) 10 /* aka m28byte */
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#define A_M94 (UTINY) 11 /* aka m94byte */
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#define A_M108 (UTINY) 12 /* aka m108byte */
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#define A_Ma16 (UTINY) 13 /* aka m16&16 */
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#define A_Ma32 (UTINY) 14 /* aka m32&32 */
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#define A_Mb (UTINY) 15 /* aka m8,r/m8,moffs8 */
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#define A_Md (UTINY) 16 /* aka m32,r/m32,moffs32 */
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#define A_Mi16 (UTINY) 17 /* aka m16int */
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#define A_Mi32 (UTINY) 18 /* aka m32int */
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#define A_Mi64 (UTINY) 19 /* aka m64int */
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#define A_Mi80 (UTINY) 20 /* aka m80dec */
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#define A_Mp16 (UTINY) 21 /* aka m16:16 */
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#define A_Mp32 (UTINY) 22 /* aka m16:32 */
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#define A_Mr32 (UTINY) 23 /* aka m32real */
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#define A_Mr64 (UTINY) 24 /* aka m64real */
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#define A_Mr80 (UTINY) 25 /* aka m80real */
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#define A_Ms (UTINY) 26 /* aka m16&32 */
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#define A_Mw (UTINY) 27 /* aka m16,r/m16,moffs16 */
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#define A_I (UTINY) 28 /* aka imm8,imm16,imm32 */
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#define A_J (UTINY) 29 /* aka rel8,rel16,rel32 */
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#define A_K (UTINY) 30 /* aka ptr16:16,ptr16:32 */
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#define A_V (UTINY) 31 /* aka ST,push onto ST, ST(i) */
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/* allowable DCD_IDENTIFIER'S for byte registers */
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#define A_AL (USHORT)0
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#define A_CL (USHORT)1
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#define A_DL (USHORT)2
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#define A_BL (USHORT)3
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#define A_AH (USHORT)4
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#define A_CH (USHORT)5
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#define A_DH (USHORT)6
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#define A_BH (USHORT)7
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/* allowable DCD_IDENTIFIER'S for word registers */
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#define A_AX (USHORT)0
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#define A_CX (USHORT)1
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#define A_DX (USHORT)2
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#define A_BX (USHORT)3
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#define A_SP (USHORT)4
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#define A_BP (USHORT)5
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#define A_SI (USHORT)6
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#define A_DI (USHORT)7
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/* allowable DCD_IDENTIFIER'S for double word registers */
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#define A_EAX (USHORT)0
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#define A_ECX (USHORT)1
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#define A_EDX (USHORT)2
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#define A_EBX (USHORT)3
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#define A_ESP (USHORT)4
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#define A_EBP (USHORT)5
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#define A_ESI (USHORT)6
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#define A_EDI (USHORT)7
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/* allowable DCD_IDENTIFIER'S for segment registers */
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/* allowable DCD_SEGMENT_ID'S for segment addressing registers */
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#define A_ES (USHORT)0
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#define A_CS (USHORT)1
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#define A_SS (USHORT)2
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#define A_DS (USHORT)3
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#define A_FS (USHORT)4
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#define A_GS (USHORT)5
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/* allowable DCD_IDENTIFIER'S for control registers */
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#define A_CR0 (USHORT)0
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#define A_CR1 (USHORT)1
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#define A_CR2 (USHORT)2
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#define A_CR3 (USHORT)3
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#define A_CR4 (USHORT)4
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#define A_CR5 (USHORT)5
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#define A_CR6 (USHORT)6
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#define A_CR7 (USHORT)7
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/* allowable DCD_IDENTIFIER'S for debug registers */
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#define A_DR0 (USHORT)0
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#define A_DR1 (USHORT)1
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#define A_DR2 (USHORT)2
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#define A_DR3 (USHORT)3
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#define A_DR4 (USHORT)4
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#define A_DR5 (USHORT)5
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#define A_DR6 (USHORT)6
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#define A_DR7 (USHORT)7
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/* allowable DCD_IDENTIFIER'S for test registers */
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#define A_TR0 (USHORT)0
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#define A_TR1 (USHORT)1
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#define A_TR2 (USHORT)2
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#define A_TR3 (USHORT)3
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#define A_TR4 (USHORT)4
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#define A_TR5 (USHORT)5
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#define A_TR6 (USHORT)6
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#define A_TR7 (USHORT)7
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/* allowable DCD_IDENTIFIER'S for memory addressing type */
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/* <addr size><mode><r/m> */
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#define A_1600 (USHORT) 0 /* [BX + SI] */
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#define A_1601 (USHORT) 1 /* [BX + DI] */
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#define A_1602 (USHORT) 2 /* [BP + SI] */
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#define A_1603 (USHORT) 3 /* [BP + DI] */
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#define A_1604 (USHORT) 4 /* [SI] */
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#define A_1605 (USHORT) 5 /* [DI] */
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#define A_1606 (USHORT) 6 /* [d16] */
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#define A_1607 (USHORT) 7 /* [BX] */
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#define A_1610 (USHORT) 8 /* [BX + SI + d8] */
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#define A_1611 (USHORT) 9 /* [BX + DI + d8] */
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#define A_1612 (USHORT)10 /* [BP + SI + d8] */
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#define A_1613 (USHORT)11 /* [BP + DI + d8] */
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#define A_1614 (USHORT)12 /* [SI + d8] */
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#define A_1615 (USHORT)13 /* [DI + d8] */
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#define A_1616 (USHORT)14 /* [BP + d8] */
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#define A_1617 (USHORT)15 /* [BX + d8] */
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#define A_1620 (USHORT)16 /* [BX + SI + d16] */
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#define A_1621 (USHORT)17 /* [BX + DI + d16] */
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#define A_1622 (USHORT)18 /* [BP + SI + d16] */
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#define A_1623 (USHORT)19 /* [BP + DI + d16] */
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#define A_1624 (USHORT)20 /* [SI + d16] */
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#define A_1625 (USHORT)21 /* [DI + d16] */
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#define A_1626 (USHORT)22 /* [BP + d16] */
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#define A_1627 (USHORT)23 /* [BX + d16] */
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/* <addr size><mode><r/m> */
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#define A_3200 (USHORT)24 /* [EAX] */
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#define A_3201 (USHORT)25 /* [ECX] */
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#define A_3202 (USHORT)26 /* [EDX] */
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#define A_3203 (USHORT)27 /* [EBX] */
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#define A_3205 (USHORT)28 /* [d32] */
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#define A_3206 (USHORT)29 /* [ESI] */
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#define A_3207 (USHORT)30 /* [EDI] */
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#define A_3210 (USHORT)31 /* [EAX + d8] */
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#define A_3211 (USHORT)32 /* [ECX + d8] */
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#define A_3212 (USHORT)33 /* [EDX + d8] */
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#define A_3213 (USHORT)34 /* [EBX + d8] */
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#define A_3215 (USHORT)35 /* [EBP + d8] */
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#define A_3216 (USHORT)36 /* [ESI + d8] */
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#define A_3217 (USHORT)37 /* [EDI + d8] */
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#define A_3220 (USHORT)38 /* [EAX + d32] */
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#define A_3221 (USHORT)39 /* [ECX + d32] */
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#define A_3222 (USHORT)40 /* [EDX + d32] */
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#define A_3223 (USHORT)41 /* [EBX + d32] */
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#define A_3225 (USHORT)42 /* [EBP + d32] */
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#define A_3226 (USHORT)43 /* [ESI + d32] */
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#define A_3227 (USHORT)44 /* [EDI + d32] */
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/* <addr size><S=SIB form><mode><base> */
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#define A_32S00 (USHORT)45 /* [EAX + si] */
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#define A_32S01 (USHORT)46 /* [ECX + si] */
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#define A_32S02 (USHORT)47 /* [EDX + si] */
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#define A_32S03 (USHORT)48 /* [EBX + si] */
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#define A_32S04 (USHORT)49 /* [ESP + si] */
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#define A_32S05 (USHORT)50 /* [d32 + si] */
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#define A_32S06 (USHORT)51 /* [ESI + si] */
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#define A_32S07 (USHORT)52 /* [EDI + si] */
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#define A_32S10 (USHORT)53 /* [EAX + si + d8] */
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#define A_32S11 (USHORT)54 /* [ECX + si + d8] */
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#define A_32S12 (USHORT)55 /* [EDX + si + d8] */
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#define A_32S13 (USHORT)56 /* [EBX + si + d8] */
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#define A_32S14 (USHORT)57 /* [ESP + si + d8] */
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#define A_32S15 (USHORT)58 /* [EBP + si + d8] */
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#define A_32S16 (USHORT)59 /* [ESI + si + d8] */
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#define A_32S17 (USHORT)60 /* [EDI + si + d8] */
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#define A_32S20 (USHORT)61 /* [EAX + si + d32] */
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#define A_32S21 (USHORT)62 /* [ECX + si + d32] */
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#define A_32S22 (USHORT)63 /* [EDX + si + d32] */
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#define A_32S23 (USHORT)64 /* [EBX + si + d32] */
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#define A_32S24 (USHORT)65 /* [ESP + si + d32] */
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#define A_32S25 (USHORT)66 /* [EBP + si + d32] */
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#define A_32S26 (USHORT)67 /* [ESI + si + d32] */
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#define A_32S27 (USHORT)68 /* [EDI + si + d32] */
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/* memory address directly encoded in instruction */
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#define A_MOFFS16 (USHORT)69 /* [d16] */
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#define A_MOFFS32 (USHORT)70 /* [d32] */
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/* <addr size><XLT>, xlat addressing form */
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#define A_16XLT (USHORT)71 /* [BX + AL] */
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#define A_32XLT (USHORT)72 /* [EBX + AL] */
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/* <addr size><ST><SRC|DST>, string addressing forms */
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#define A_16STSRC (USHORT)73 /* [SI] */
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#define A_32STSRC (USHORT)74 /* [ESI] */
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#define A_16STDST (USHORT)75 /* [DI] */
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#define A_32STDST (USHORT)76 /* [EDI] */
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/* allowable DCD_SUBTYPE'S for memory addressing sub type */
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/* <ss><index> */
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#define A_SINO (UTINY) 0 /* No SIB byte */
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#define A_SI00 (UTINY) 1 /* EAX */
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#define A_SI01 (UTINY) 2 /* ECX */
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#define A_SI02 (UTINY) 3 /* EDX */
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#define A_SI03 (UTINY) 4 /* EBX */
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#define A_SI04 (UTINY) 5 /* none */
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#define A_SI05 (UTINY) 6 /* EBP */
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#define A_SI06 (UTINY) 7 /* ESI */
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#define A_SI07 (UTINY) 8 /* EDI */
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#define A_SI10 (UTINY) 9 /* EAX x 2 */
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#define A_SI11 (UTINY)10 /* ECX x 2 */
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#define A_SI12 (UTINY)11 /* EDX x 2 */
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#define A_SI13 (UTINY)12 /* EBX x 2 */
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#define A_SI14 (UTINY)13 /* undefined */
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#define A_SI15 (UTINY)14 /* EBP x 2 */
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#define A_SI16 (UTINY)15 /* ESI x 2 */
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#define A_SI17 (UTINY)16 /* EDI x 2 */
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#define A_SI20 (UTINY)17 /* EAX x 4 */
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#define A_SI21 (UTINY)18 /* ECX x 4 */
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#define A_SI22 (UTINY)19 /* EDX x 4 */
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#define A_SI23 (UTINY)20 /* EBX x 4 */
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#define A_SI24 (UTINY)21 /* undefined */
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#define A_SI25 (UTINY)22 /* EBP x 4 */
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#define A_SI26 (UTINY)23 /* ESI x 4 */
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#define A_SI27 (UTINY)24 /* EDI x 4 */
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#define A_SI30 (UTINY)25 /* EAX x 8 */
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#define A_SI31 (UTINY)26 /* ECX x 8 */
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#define A_SI32 (UTINY)27 /* EDX x 8 */
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#define A_SI33 (UTINY)28 /* EBX x 8 */
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#define A_SI34 (UTINY)29 /* undefined */
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#define A_SI35 (UTINY)30 /* EBP x 8 */
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#define A_SI36 (UTINY)31 /* ESI x 8 */
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#define A_SI37 (UTINY)32 /* EDI x 8 */
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/* allowable DCD_IDENTIFIER'S for immediates */
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#define A_IMMC (USHORT)0 /* constant */
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#define A_IMMB (USHORT)1 /* byte */
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#define A_IMMW (USHORT)2 /* word */
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#define A_IMMD (USHORT)3 /* double word */
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#define A_IMMWB (USHORT)4 /* word <- byte */
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#define A_IMMDB (USHORT)5 /* double word <- byte */
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/* allowable DCD_IDENTIFIER'S for co-processor registers */
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#define A_ST (USHORT)0 /* Stack Top */
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#define A_STP (USHORT)1 /* Push onto Stack Top */
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#define A_STI (USHORT)2 /* Stack Register relative to Stack Top */
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/* allowable DCD_ADDRESSABILITY'S
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The operand addressability rules, bit encoded as follows:-
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Bit 0 = 1 ==> is source argument.
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Bit 1 = 1 ==> is destination argument.
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*/
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#define AA_ 0
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#define AA_R 1
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#define AA_W 2
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#define AA_RW 3
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/*
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Macros to access operand values.
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All take pointer to DECODED_ARG as their argument.
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*/
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#define DCD_IDENTIFIER(p) ((p)->identifier)
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#define DCD_ADDRESSABILITY(p) ((p)->addressability)
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#define DCD_SUBTYPE(p) ((p)->sub_id)
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#define DCD_SEGMENT_ID(p) ((p)->arg_values[0])
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#define DCD_DISP(p) ((p)->arg_values[1])
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#define DCD_IMMED1(p) ((p)->arg_values[0])
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#define DCD_IMMED2(p) ((p)->arg_values[1])
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#define DCD_INDEX(p) ((p)->arg_values[0])
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