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258 lines
6.9 KiB
258 lines
6.9 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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iodevice.h
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Abstract:
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This module contains definitions to access the IO devices in the
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Alpha Jensen system.
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Author:
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Lluis Abello (lluis) 03-Jan-1991
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Environment:
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Revision History:
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21-May-1992 John DeRosa [DEC]
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Modified Lluis's original Jazz file for Alpha/Jensen.
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--*/
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#ifndef _IODEVICE_
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#define _IODEVICE_
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//#include <jnsndef.h>
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//#include <jnsnrtc.h>
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#include "machdef.h"
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#include <jnsnserp.h>
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#include <eisa.h> // for the isp interrupt controller init.
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//
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// Not defined in the Alpha/Jensen firmware. The one place where this was
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// used, the floppy driver, now uses WaitForFloppyInterrupt.
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//
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#if 0
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ARC_STATUS
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FwWaitForDeviceInterrupt(
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USHORT InterruptMask,
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ULONG Timeout
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);
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#endif // 0
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//
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// HAE and SYSCTL structure, values, and pointers.
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//
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typedef struct _HAE_REGISTER {
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UCHAR Reserved : 1;
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UCHAR UpperEisaAdd : 7;
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} HAE_REGISTER, *PHAE_REGISTER;
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#define HAE ( (volatile PHAE_REGISTER) HAE_VIRTUAL_BASE )
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typedef struct _SYSCTL_REGISTER {
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UCHAR Reserved : 2;
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UCHAR MemConfig : 2;
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UCHAR LED : 4;
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} SYSCTL_REGISTER, *PSYSCTL_REGISTER;
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#define SYSCTL ( (volatile PSYSCTL_REGISTER) SYSCTL_VIRTUAL_BASE )
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//
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// COM controller register pointer definitions.
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//
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#define SP1_READ ( (volatile PSP_READ_REGISTERS) COMPORT1_VIRTUAL_BASE )
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#define SP1_WRITE ( (volatile PSP_WRITE_REGISTERS)COMPORT1_VIRTUAL_BASE )
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#define SP2_READ ( (volatile PSP_READ_REGISTERS) COMPORT2_VIRTUAL_BASE )
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#define SP2_WRITE ( (volatile PSP_WRITE_REGISTERS)COMPORT2_VIRTUAL_BASE )
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//
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// PARALLEL port write registers.
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//
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typedef struct _PARALLEL_WRITE_REGISTERS {
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UCHAR Data;
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UCHAR Invalid;
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UCHAR Control;
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} PARALLEL_WRITE_REGISTERS, * PPARALLEL_WRITE_REGISTERS;
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//
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// PARALLEL port read Registers
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//
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typedef struct _PARALLEL_READ_REGISTERS {
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UCHAR Data;
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UCHAR Status;
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UCHAR Control;
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} PARALLEL_READ_REGISTERS,* PPARALLEL_READ_REGISTERS;
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//
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// PARALLEL controller register pointer definitions.
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//
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#define PARALLEL_READ ( (volatile PPARALLEL_READ_REGISTERS)PARALLEL_VIRTUAL_BASE )
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#define PARALLEL_WRITE ( (volatile PPARALLEL_WRITE_REGISTERS)PARALLEL_VIRTUAL_BASE )
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//
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// FLOPPY read registers.
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//
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typedef struct _FLOPPY_READ_REGISTERS {
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UCHAR StatusA;
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UCHAR StatusB;
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UCHAR DigitalOutput;
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UCHAR Reserved1;
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UCHAR MainStatus;
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UCHAR Fifo;
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UCHAR Reserved2;
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UCHAR DigitalInput;
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} FLOPPY_READ_REGISTERS, * PFLOPPY_READ_REGISTERS;
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//
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// FLOPPY write registers.
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//
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typedef struct _FLOPPY_WRITE_REGISTERS {
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UCHAR StatusA;
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UCHAR StatusB;
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UCHAR DigitalOutput;
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UCHAR Reserved1;
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UCHAR DataRateSelect;
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UCHAR Fifo;
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UCHAR Reserved2;
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UCHAR ConfigurationControl;
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} FLOPPY_WRITE_REGISTERS, * PFLOPPY_WRITE_REGISTERS ;
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//
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// FLOPPY controller register pointer definitions.
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//
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#define FLOPPY_READ ((volatile PFLOPPY_READ_REGISTERS)FLOPPY_VIRTUAL_BASE)
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#define FLOPPY_WRITE ((volatile PFLOPPY_WRITE_REGISTERS)FLOPPY_VIRTUAL_BASE)
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//
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// KEYBOARD write registers.
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//
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typedef struct _KEYBOARD_WRITE_REGISTERS {
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UCHAR Data; // port 60H
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UCHAR Filler[3];
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UCHAR Command; // port 64H
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} KEYBOARD_WRITE_REGISTERS, * PKEYBOARD_WRITE_REGISTERS;
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//
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// KEYBOARD read Registers
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//
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typedef struct _KEYBOARD_READ_REGISTERS {
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UCHAR Data; // port 60H
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UCHAR Filler[3];
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UCHAR Status; // port 64H
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} KEYBOARD_READ_REGISTERS, * PKEYBOARD_READ_REGISTERS;
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//
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// KEYBOARD controller register pointer definitions.
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//
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#define KEYBOARD_READ ( (volatile PKEYBOARD_READ_REGISTERS)KEYBOARD_VIRTUAL_BASE )
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#define KEYBOARD_WRITE ( (volatile PKEYBOARD_WRITE_REGISTERS)KEYBOARD_VIRTUAL_BASE)
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//
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// Keyboard circular buffer type definition.
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//
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#define KBD_BUFFER_SIZE 32
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typedef struct _KEYBOARD_BUFFER {
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volatile UCHAR Buffer[KBD_BUFFER_SIZE];
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volatile UCHAR ReadIndex;
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volatile UCHAR WriteIndex;
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} KEYBOARD_BUFFER, *PKEYBOARD_BUFFER;
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#define TIME_OUT 0xdead
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//
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// EISA Stuff
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// ***** temp **** this should be replaced by the definition in
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// "ntos\inc\eisa.h" as soon as it is complete.
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//
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typedef struct _EISA {
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UCHAR Dma1Ch0Address; //0x00
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UCHAR Dma1Ch0Count; //0x01
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UCHAR Dma1Ch1Address; //0x02
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UCHAR Dma1Ch1Count; //0x03
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UCHAR Dma1Ch2Address; //0x04
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UCHAR Dma1Ch2Count; //0x05
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UCHAR Dma1Ch3Address; //0x06
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UCHAR Dma1Ch3Count; //0x07
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UCHAR Dma1StatusCommand; //0x08
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UCHAR Dma1Request; //0x09
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UCHAR Dma1SingleMask; //0x0a
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UCHAR Dma1Mode; //0x0b
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UCHAR Dma1ClearBytePointer; //0x0c
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UCHAR Dma1MasterClear; //0x0d
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UCHAR Dma1ClearMask; //0x0e
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UCHAR Dma1AllMask; //0x0f
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ULONG Fill01; //0x10-13
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ULONG Fill02; //0x14-17
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ULONG Fill03; //0x18-1b
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ULONG Fill04; //0x1c-1f
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UCHAR Int1Control; //0x20
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UCHAR Int1Mask; //0x21
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USHORT Fill10; //0x22-23
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ULONG Fill11; //0x24
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ULONG Fill12; //0x28
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ULONG Fill13; //0x2c
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ULONG Fill14; //0x30
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ULONG Fill15; //0x34
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ULONG Fill16; //0x38
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ULONG Fill17; //0x3c
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UCHAR IntTimer1SystemClock; //0x40
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UCHAR IntTimer1RefreshRequest; //0x41
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UCHAR IntTimer1SpeakerTone; //0x42
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UCHAR IntTimer1CommandMode; //0x43
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ULONG Fill20; //0x44
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UCHAR IntTimer2FailsafeClock; //0x48
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UCHAR IntTimer2Reserved; //0x49
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UCHAR IntTimer2CPUSpeeedCtrl; //0x4a
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UCHAR IntTimer2CommandMode; //0x4b
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ULONG Fill30; //0x4c
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ULONG Fill31; //0x50
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ULONG Fill32; //0x54
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ULONG Fill33; //0x58
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ULONG Fill34; //0x5c
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UCHAR Fill35; //0x60
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UCHAR NMIStatus; //0x61
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UCHAR Fill40; //0x62
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UCHAR Fill41; //0x63
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ULONG Fill42; //0x64
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ULONG Fill43; //0x68
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ULONG Fill44; //0x6c
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UCHAR NMIEnable; //0x70
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}EISA, * PEISA;
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#define ISP ( (volatile PEISA) EISA_IO_VIRTUAL_BASE )
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#define EISA_CONTROL ( (volatile PEISA_CONTROL) EISA_IO_VIRTUAL_BASE )
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#endif // _IODEVICE_
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