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547 lines
12 KiB
547 lines
12 KiB
// -----------------------------------------------------------------------------
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//
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// Copyright (c) 1992 Olivetti
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//
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// File: arceisa.h
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//
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// Description: ARC-EISA Addendum Structures and Defines.
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//
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// -----------------------------------------------------------------------------
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//
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// Define the EISA firmware entry points
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//
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typedef enum _EISA_FIRMWARE_ENTRY
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{
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ProcessEOIRoutine,
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TestIntRoutine,
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RequestDMARoutine,
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AbortDMARoutine,
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GetDMAStatusRoutine,
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DoLockRoutine,
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RequestBusMasterRoutine,
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ReleaseBusMasterRoutine,
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RequestCpuAccessToBusRoutine,
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ReleaseCpuAccessToBusRoutine,
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FlushCacheRoutine,
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InvalidateCacheRoutine,
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ReservedRoutine,
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BeginCriticalSectionRoutine,
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EndCriticalSectionRoutine,
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GenerateToneRoutine,
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FlushWriteBuffersRoutine,
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YieldRoutine,
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StallProcessorRoutine,
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MaximumEisaRoutine
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} EISA_FIRMWARE_ENTRY;
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//
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// Define EISA interrupt functions
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//
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typedef
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ARC_STATUS
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(*PEISA_PROCESS_EOI_RTN)
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(
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IN ULONG BusNumber,
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IN USHORT IRQ
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);
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typedef
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BOOLEAN_ULONG
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(*PEISA_TEST_INT_RTN)
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(
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IN ULONG BusNumber,
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IN USHORT IRQ
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);
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//
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// Define EISA DMA functions
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//
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typedef enum _DMA_TRANSFER_TYPE
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{
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DmaVerify,
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DmaWrite,
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DmaRead,
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DmaMaxType
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} DMA_TRANSFER_TYPE, *PDMA_TRANSFER_TYPE;
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typedef enum _DMA_TRANSFER_MODE
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{
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DmaDemand,
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DmaSingle,
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DmaBlock,
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DmaCascade,
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DmaMaxMode
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} DMA_TRANSFER_MODE, *PDMA_TRANSFER_MODE;
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typedef enum _DMA_TIMING_MODE
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{
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DmaIsaCompatible,
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DmaTypeA,
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DmaTypeB,
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DmaBurst,
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DmaMaxTiming
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} DMA_TIMING_MODE, *PDMA_TIMING_MODE;
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typedef enum _DMA_ADDRESSING_MODE
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{
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Dma8Bit,
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Dma16sBit,
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Dma32Bit,
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Dma16Bit,
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DmaMaxAddressing
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} DMA_ADDRESSING_MODE, *PDMA_ADDRESSING_MODE;
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typedef struct _DMA_TRANSFER
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{
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DMA_TRANSFER_MODE TransferMode;
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ULONG ChannelNumber;
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DMA_TRANSFER_TYPE TransferType;
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ULONG Size;
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PVOID Buffer;
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} DMA_TRANSFER, *PDMA_TRANSFER;
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typedef struct _DMA_STATUS
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{
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BOOLEAN_ULONG CompleteTransfer;
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ULONG ByteTransferred;
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} DMA_STATUS, *PDMA_STATUS;
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typedef
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ARC_STATUS
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(*PEISA_REQ_DMA_XFER_RTN)
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(
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IN ULONG BusNumber,
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IN PDMA_TRANSFER pDmaTransfer
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);
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typedef
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ARC_STATUS
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(*PEISA_ABORT_DMA_RTN)
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(
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IN ULONG BusNumber,
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IN PDMA_TRANSFER pDmaTransfer
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);
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typedef
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ARC_STATUS
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(*PEISA_DMA_XFER_STATUS_RTN)
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(
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IN ULONG BusNumber,
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IN PDMA_TRANSFER pDmaTransfer,
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OUT PDMA_STATUS pDmaStatus
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);
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//
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// Define EISA lock function
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//
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typedef enum _EISA_LOCK_OPERATION
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{
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Exchange,
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LockMaxOperation
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} EISA_LOCK_OPERATION;
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typedef enum _SEMAPHORE_SIZE
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{
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ByteSemaphore,
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HalfWordSemaphore,
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WordSemaphore,
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MaxSemaphore
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} SEMAPHORE_SIZE;
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typedef
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ARC_STATUS
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(*PEISA_LOCK_RTN)
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(
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IN ULONG BusNumber,
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IN EISA_LOCK_OPERATION Operation,
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IN PVOID Semaphore,
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IN SEMAPHORE_SIZE SemaphoreSize,
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IN PVOID OperationArgument,
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OUT PVOID OperationResult
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);
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//
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// Define EISA bus master functions.
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//
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typedef enum _BUS_MASTER_TRANSFER_TYPE
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{
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BusMasterWrite,
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BusMasterRead,
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BusMasterMaxType
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} BUS_MASTER_TRANSFER_TYPE, *PBUS_MASTER_TRANSFER_TYPE;
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typedef enum _ADDRESS_RESTRICTION
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{
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LimitNone,
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Limit16Mb,
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Limit4Gb,
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LimitMax
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} ADDRESS_RESTRICTION, *PADDRESS_RESTRICTION;
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typedef struct _BUS_MASTER_TRANSFER
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{
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ADDRESS_RESTRICTION Limit;
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ULONG SlotNumber;
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BUS_MASTER_TRANSFER_TYPE TransferType;
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ULONG Size;
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PVOID Buffer;
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} BUS_MASTER_TRANSFER, *PBUS_MASTER_TRANSFER;
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typedef
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ARC_STATUS
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(*PEISA_REQUEST_BUS_MASTER_RTN)
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(
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IN ULONG BusNumber,
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IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
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OUT ULONG *TranslateBufferAddress
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);
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typedef
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ARC_STATUS
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(*PEISA_RELEASE_BUS_MASTER_RTN)
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(
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IN ULONG BusNumber,
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IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
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IN ULONG TranslateBufferAddress
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);
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//
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// Define EISA slave functions
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//
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typedef struct _SLAVE_TRANSFER
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{
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ULONG SlotNumber;
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ULONG Size;
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ULONG Buffer;
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} SLAVE_TRANSFER, *PSLAVE_TRANSFER;
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typedef
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ARC_STATUS
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(*PEISA_REQUEST_CPU_TO_BUS_ACCESS_RTN)
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(
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IN ULONG BusNumber,
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IN PSLAVE_TRANSFER pSlaveTransfer,
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OUT PVOID *TranslatedBufferAddress
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);
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typedef
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ARC_STATUS
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(*PEISA_RELEASE_CPU_TO_BUS_ACCESS_RTN)
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(
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IN ULONG BusNumber,
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IN PSLAVE_TRANSFER pSlaveTransfer,
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IN PVOID TranslateBufferAddress
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);
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typedef
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VOID
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(*PEISA_FLUSH_CACHE_RTN)
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(
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IN PVOID Address,
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IN ULONG Length
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);
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typedef
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VOID
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(*PEISA_INVALIDATE_CACHE_RTN)
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(
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IN PVOID Address,
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IN ULONG Length
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);
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typedef
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VOID
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(*PEISA_RESERVED_RTN)
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(
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VOID
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);
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typedef
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VOID
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(*PEISA_BEGIN_CRITICAL_SECTION_RTN)
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(
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VOID
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);
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typedef
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VOID
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(*PEISA_END_CRITICAL_SECTION_RTN)
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(
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VOID
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);
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typedef
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ARC_STATUS
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(*PEISA_GENERATE_TONE_RTN)
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(
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IN ULONG Frequency,
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IN ULONG Duration
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);
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typedef
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VOID
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(*PEISA_FLUSH_WRITE_BUFFER_RTN)
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(
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VOID
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);
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typedef
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BOOLEAN_ULONG
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(*PEISA_YIELD_RTN)
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(
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VOID
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);
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typedef
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VOID
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(*PEISA_STALL_PROCESSOR_RTN)
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(
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IN ULONG Duration
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);
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//
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// Define EISA callback vectors prototypes.
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//
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ARC_STATUS
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EisaProcessEndOfInterrupt
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(
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IN ULONG BusNumber,
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IN USHORT Irq
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);
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BOOLEAN_ULONG
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EisaTestEisaInterrupt
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(
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IN ULONG BusNumber,
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IN USHORT Irq
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);
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ARC_STATUS
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EisaRequestEisaDmaTransfer
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(
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IN ULONG BusNumber,
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IN PDMA_TRANSFER pDmaTransfer
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);
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ARC_STATUS
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EisaAbortEisaDmaTransfer
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(
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IN ULONG BusNumber,
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IN PDMA_TRANSFER pDmaTransfer
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);
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ARC_STATUS
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EisaGetEisaDmaTransferStatus
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(
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IN ULONG BusNumber,
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IN PDMA_TRANSFER pDmaTransfer,
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OUT PDMA_STATUS pDmaStatus
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);
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ARC_STATUS
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EisaDoLockedOperation
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(
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IN ULONG BusNumber,
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IN EISA_LOCK_OPERATION Operation,
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IN PVOID Semaphore,
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IN SEMAPHORE_SIZE SemaphoreSize,
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IN PVOID OperationArgument,
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OUT PVOID OperationResult
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);
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ARC_STATUS
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EisaRequestEisaBusMasterTransfer
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(
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IN ULONG BusNumber,
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IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
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OUT ULONG *TranslatedBufferAddress
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);
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ARC_STATUS
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EisaReleaseEisaBusMasterTransfer
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(
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IN ULONG BusNumber,
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IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
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IN ULONG TranslatedBufferAddress
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);
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ARC_STATUS
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EisaRequestCpuAccessToEisaBus
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(
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IN ULONG BusNumber,
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IN PSLAVE_TRANSFER pSlaveTransfer,
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OUT PVOID *TranslatedAddress
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);
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ARC_STATUS
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EisaReleaseCpuAccessToEisaBus
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(
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IN ULONG BusNumber,
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IN PSLAVE_TRANSFER pSlaveTransfer,
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IN PVOID TranslatedAddress
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);
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VOID
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EisaFlushCache
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(
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IN PVOID Address,
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IN ULONG Length
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);
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VOID
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EisaInvalidateCache
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(
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IN PVOID Address,
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IN ULONG Length
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);
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VOID
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EisaBeginCriticalSection
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(
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IN VOID
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);
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VOID
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EisaEndCriticalSection
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(
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IN VOID
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);
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VOID
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EisaFlushWriteBuffers
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(
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VOID
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);
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ARC_STATUS
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EisaGenerateTone
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(
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IN ULONG Frequency,
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IN ULONG Duration
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);
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BOOLEAN_ULONG
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EisaYield
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(
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VOID
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);
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VOID
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EisaStallProcessor
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(
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IN ULONG Duration
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);
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//
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// Define macros that call the EISA firmware routines indirectly through the
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// EISA firmware vector and provide type checking of argument values.
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//
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#define ArcEisaProcessEndOfInterrupt(BusNumber, IRQ) \
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((PEISA_PROCESS_EOI_RTN)(SYSTEM_BLOCK->Adapter0Vector[ProcessEOIRoutine])) \
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((BusNumber), (IRQ))
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#define ArcEisaTestEisaInterupt(BusNumber, IRQ) \
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((PEISA_TEST_INT_RTN)(SYSTEM_BLOCK->Adapter0Vector[TestIntRoutine])) \
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((BusNumber), (IRQ))
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#define ArcEisaRequestEisaDmaTransfer(BusNumber, pDmaTransfer) \
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((PEISA_REQ_DMA_XFER_RTN)(SYSTEM_BLOCK->Adapter0Vector[RequestDMARoutine])) \
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((BusNumber), (pDmaTransfer))
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#define ArcEisaAbortEisaDmaTransfer(BusNumber, pDmaTransfer) \
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((PEISA_ABORT_DMA_RTN)(SYSTEM_BLOCK->Adapter0Vector[AbortDMARoutine])) \
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((BusNumber), (pDmaTransfer))
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#define ArcEisaGetEisaDmaTransferStatus(BusNumber, pDmaTransfer, pDmaStatus) \
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((PEISA_DMA_XFER_STATUS_RTN)(SYSTEM_BLOCK->Adapter0Vector[GetDMAStatusRoutine])) \
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((BusNumber), (pDmaTransfer), (pDmaStatus))
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#define ArcEisaDoLockedOperation(BusNumber, Operation, Semaphore, SemaphoreSize, OperationArgument, OperationResult) \
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((PEISA_LOCK_RTN)(SYSTEM_BLOCK->Adapter0Vector[DoLockRoutine])) \
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((BusNumber), (Operation), (Semaphore), (SemaphoreSize), (OperationArgument), (OperationResult))
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#define ArcEisaRequestEisaBusMasterTransferCPUAddressToBusAddress(BusNumber, pBusMasterTransfer, TranslateBufferAddress) \
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((PEISA_REQUEST_BUS_MASTER_RTN)(SYSTEM_BLOCK->Adapter0Vector[RequestBusMasterRoutine])) \
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((BusNumber), (pBusMasterTransfer), (TranslateBufferAddress))
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#define ArcEisaReleaseEisaBusMasterTransfer(BusNumber, pBusMasterTransfer, TranslateBufferAddress) \
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((PEISA_RELEASE_BUS_MASTER_RTN)(SYSTEM_BLOCK->Adapter0Vector[ReleaseBusMasterRoutine])) \
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((BusNumber), (pBusMasterTransfer), (TranslateBufferAddress))
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#define ArcEisaRequestCpuAccessToEisaBus(BusNumber, pSlaveTransfer, TranslatedBufferAddress) \
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((PEISA_REQUEST_CPU_TO_BUS_ACCESS_RTN)(SYSTEM_BLOCK->Adapter0Vector[RequestCpuAccessToBusRoutine])) \
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((BusNumber), (pSlaveTransfer), (TranslatedBufferAddress))
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#define ArcEisaReleaseCpuAccessToEisaBus(BusNumber, pSlaveTransfer, TranslatedBufferAddress) \
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((PEISA_RELEASE_CPU_TO_BUS_ACCESS_RTN)(SYSTEM_BLOCK->Adapter0Vector[ReleaseCpuAccessToBusRoutine])) \
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((BusNumber), (pSlaveTransfer), (TranslatedBufferAddress))
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#define ArcEisaFlushCache(Address, Length) \
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((PEISA_FLUSH_CACHE_RTN)(SYSTEM_BLOCK->Adapter0Vector[FlushCacheRoutine])) \
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((Address), (Length))
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#define ArcEisaInvalidateCache(Address, Length) \
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((PEISA_INVALIDATE_CACHE_RTN)(SYSTEM_BLOCK->Adapter0Vector[InvalidateCacheRoutine])) \
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((Address), (Length))
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#define ArcEisaBeginCriticalSection() \
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((PEISA_BEGIN_CRITICAL_SECTION_RTN)(SYSTEM_BLOCK->Adapter0Vector[BeginCriticalSectionRoutine]))()
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#define ArcEisaEndCriticalSection() \
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((PEISA_END_CRITICAL_SECTION_RTN)(SYSTEM_BLOCK->Adapter0Vector[EndCriticalSectionRoutine]))()
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#define ArcEisaGenerateTone() \
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((PEISA_GENERATE_TONE_RTN)(SYSTEM_BLOCK->Adapter0Vector[GenerateToneRoutine])) \
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((Freqency), (Duration))
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#define ArcEisaFlushWriteBuffers() \
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((PEISA_FLUSH_WRITE_BUFFER_RTN)(SYSTEM_BLOCK->Adapter0Vector[FlushWriteBuffersRoutine]))()
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#define ArcEisaYield() \
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((PEISA_YIELD_RTN)(SYSTEM_BLOCK->Adapter0Vector[YieldRoutine]))()
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#define ArcEisaStallProcessor(Duration) \
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((PEISA_STALL_PROCESSOR_RTN)(SYSTEM_BLOCK->Adapter0Vector[StallProcessorRoutine])) \
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(Duration)
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//
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// General OMF defines
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//
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#define OMF_BLOCK_SIZE 512 // OMF block size in bytes
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#define OMF_MAX_SIZE (32*1024*1024) // max OMF size in bytes
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#define OMF_MAX_FILE_LEN ((16*1024*1024)/(1<<WORD_2P2)) // (16 Mbytes max)/4
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#define OMF_MAX_FILE_LINK ((16*1024*1024)/(1<<WORD_2P2)) // (16 Mbytes max)/4
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#define OMF_ID_1ST 0x55 // 1st OMF ID
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#define OMF_ID_2ND 0x00 // 2nd OMF ID
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#define OMF_ID_3RD 0xAA // 3rd OMF ID
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#define OMF_ID_4TH 0xFF // 4th OMF ID
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#define OMF_FILE_NAME_LEN 12 // 12 chars
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//
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// Define OMF FAT file name structure
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//
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typedef struct _OMF_FAT_FILE_NAME
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{
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CHAR ProductId[7];
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CHAR Version;
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CHAR Dot;
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CHAR Extension[2];
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CHAR Revision;
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} OMF_FAT_FILE_NAME, *POMF_FAT_FILE_NAME;
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