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516 lines
12 KiB
516 lines
12 KiB
#ifdef DUO
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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duosync.c
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Abstract:
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This module contains the routines that perform synchronization
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among processors.
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Author:
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Lluis Abello (lluis) 06-Apr-1993
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Environment:
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Revision History:
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--*/
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#include "fwp.h"
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#include "iodevice.h"
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#include "led.h"
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#include "selfmap.h"
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#include "selftest.h"
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#include "ioaccess.h"
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#include "fwstring.h"
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volatile PROCESSOR_B_TASK_VECTOR ProcessorBTask;
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extern BOOLEAN ProcessorBEnabled;
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VOID
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InitializePCR(
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);
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MEMORY_TEST_DATA BMemTest1 = {
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0xA0100000,
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0x100000,
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0,
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LED_B_MEMORY_TEST_1
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};
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MEMORY_TEST_DATA BMemTest2 = {
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0x80200000,
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0x100000,
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0,
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LED_B_MEMORY_TEST_2
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};
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MEMORY_TEST_DATA BMemTest3 = {
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VIDEO_MEMORY_VIRTUAL_BASE+1280*1024, // start adr = end of visible screen
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0x200000-1280*1024, // size = rest of video memory.
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0,
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LED_VIDEOMEM
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};
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//
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// The following table defines the selftest routines that will be executed
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// by processor B.
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//
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PROCESSOR_B_TEST ProcessorBSelfTests[] = {
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{ProcessorBMemoryTest,&BMemTest1},
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{ProcessorBMemoryTest,&BMemTest2},
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{ProcessorBVideoMemoryTest,&BMemTest3},
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{NULL,0}
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};
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ULONG
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ExecuteOnProcessorB(
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IN PPROCESSOR_TASK_ROUTINE Routine,
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IN PVOID Data
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)
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/*++
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Routine Description:
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This routine puts the supplied Routine and Data in processor B task vector
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and issues an IP interrupt to processor B which will then execute
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it and set the return value.
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Arguments:
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None
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Return Value:
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None
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--*/
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{
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PPROCESSOR_B_TASK_VECTOR TaskVector;
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if (!ProcessorBEnabled) {
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return 0;
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}
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//
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// Get a non pointer to the Task Vector
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//
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TaskVector = (PPROCESSOR_B_TASK_VECTOR)&ProcessorBTask;
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TaskVector->Routine = Routine;
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TaskVector->Data = Data;
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//
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// Issue an IP interrupt to notify processor B that a task has
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// been scheduled for execution.
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//
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WRITE_REGISTER_ULONG(&DMA_CONTROL->IpInterruptRequest.Long,2);
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//
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// If timeout or Return Value indicates error, stop here.
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//
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if (WaitForIpInterrupt(5000) == FALSE) {
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FwPrint("\r\nTimeout waiting for B to execute %lx\r\n",Routine);
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}
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return (TaskVector->ReturnValue);
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}
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VOID
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ProcessorBMain(
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)
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/*++
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Routine Description:
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This is the main routine for processor B.
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It jumps here after initialization.
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The startup sequence is as follows:
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ProcessorA sets the address of this routine in the ProcessorBTask vector.
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ProcessorA Enables Processor B in the Global Configuration register.
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ProcessorA Calls WaitForIPInterrupt.
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When Processor B is enabled it runs at the PROM reset vector, it
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initializes itself and jumps to the routine pointed to by ProcessorTask
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which is this routine.
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Once here processor B Wakes up processor A by issuing an IP interrupt
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and Loops for ever waiting for IP interrupts and executing the Task
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pointed to by ProcessorBTask.
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Arguments:
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None
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Return Value:
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None
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--*/
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{
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PPROCESSOR_TASK_ROUTINE Task;
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PVOID TaskData;
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ULONG ReturnValue;
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//
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// Get a pointer to the Task Vector
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//
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PPROCESSOR_B_TASK_VECTOR TaskVector = (PPROCESSOR_B_TASK_VECTOR)&ProcessorBTask;
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//
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// Enable IP interrupts.
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// All interrupts are disabled in the psr.
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//
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WRITE_REGISTER_ULONG(&DMA_CONTROL->InterruptEnable.Long,ENABLE_IP_INTERRUPTS);
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for (;;) {
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//
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// Wake up processor A
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//
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WRITE_REGISTER_ULONG(&DMA_CONTROL->IpInterruptRequest.Long,1);
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WaitForIpInterrupt(0);
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//
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// Execute Task
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//
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Task = TaskVector->Routine;
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TaskData = TaskVector->Data;
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ReturnValue = Task(TaskData);
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TaskVector->ReturnValue = ReturnValue;
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}
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}
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ULONG
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ProcessorBMemoryTest(
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IN PMEMORY_TEST_DATA MemoryData
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)
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/*++
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Routine Description:
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This routine tests the portion of memory supplied by Data.
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Arguments:
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MemoryData - Pointer to a data structure describing the range of
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memory to be tested.
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Return Value:
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None
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--*/
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{
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PutLedDisplay(MemoryData->LedDisplayValue);
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WriteMemoryAddressTest(MemoryData->StartAddress,MemoryData->Size,MemoryData->XorPattern);
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CheckMemoryAddressTest(MemoryData->StartAddress,MemoryData->Size,MemoryData->XorPattern,MemoryData->LedDisplayValue);
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return 1;
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}
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ULONG
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ProcessorBVideoMemoryTest(
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IN PMEMORY_TEST_DATA MemoryData
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)
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/*++
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Routine Description:
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This routine tests the portion of video memory supplied by Data.
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Arguments:
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MemoryData - Pointer to a data structure describing the range of
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memory to be tested.
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Return Value:
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None
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--*/
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{
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PutLedDisplay(MemoryData->LedDisplayValue);
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WriteVideoMemoryAddressTest(MemoryData->StartAddress,MemoryData->Size);
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CheckVideoMemoryAddressTest(MemoryData->StartAddress,MemoryData->Size);
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return 1;
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}
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ULONG
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CoherencyTest(
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IN PVOID CoherentPage
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)
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/*++
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Routine Description:
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This routine performs a coherency test. This routine will be executed
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simultaneously by both processors.
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Processor A stores even bytes and Processor B stores the odd bytes.
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To make sure that cache blocks are passed back and forth, a semaphore
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locks it's access so that the cache line ping pongs from processor to
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processor.
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Arguments:
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CoherentPage. Pointer aligned to a page boundary. Which is marked
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either Exclusive or Shared in the TLB.
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The first ulong is used as the semaphore. The rest of the page
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is used as data.
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Return Value:
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Number of errors found.
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--*/
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{
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volatile PULONG Semaphore = (PULONG)CoherentPage;
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PULONG CoherentData = Semaphore+64/sizeof(ULONG);
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ULONG Counter;
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ULONG Processor;
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ULONG DataLong;
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ULONG Errors = 0;
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if (READ_REGISTER_ULONG(&DMA_CONTROL->WhoAmI.Long)) {
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//
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// Processor B
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//
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Processor = 1;
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DataLong = 0xB0B00000;
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} else {
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Processor = 0;
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DataLong = 0xA0A00000;
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}
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for (Counter = 0; Counter < (0x1000-64)/sizeof(ULONG); Counter += 2) {
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//
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// Wait for counter.
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// No need for interlocks since each processor waits
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// for a different value.
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//
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while (*Semaphore != Counter+Processor) {
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}
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*(CoherentData+Processor) = DataLong | Counter;
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*Semaphore = Counter+Processor+1;
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CoherentData += 2;
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}
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//
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// Both processors check all the data.
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//
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CoherentData = Semaphore+64/sizeof(ULONG);;
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for (Counter = 0; Counter < (0x1000-64)/sizeof(ULONG); Counter +=2) {
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if (*CoherentData != (Counter | 0xA0A00000)) {
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Errors++;
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}
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CoherentData++;
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if (*CoherentData != (Counter | 0xB0B00000)) {
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Errors++;
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}
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CoherentData++;
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}
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return Errors;
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}
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BOOLEAN
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ProcessorBSelftest(
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IN VOID
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)
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/*++
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Routine Description:
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This routine sets the different tasks to be executed by processor
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b and waits for them to complete. This routine is executed by the
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master processor.
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Arguments:
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None.
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Return Value:
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TRUE if passed FALSE otherwise
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--*/
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{
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BOOLEAN ReturnValue;
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BOOLEAN Timeout;
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//
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// Get a pointer to the Task Vector
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//
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PPROCESSOR_B_TASK_VECTOR TaskVector = (PPROCESSOR_B_TASK_VECTOR)&ProcessorBTask;
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PPROCESSOR_B_TEST ProcessorBTestList = ProcessorBSelfTests;
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//
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// Place each task of the SelftestTable in the TaskVector to be executed
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// by processor B.
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//
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while (ProcessorBTestList->Routine != NULL) {
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TaskVector->Routine = ProcessorBTestList->Routine;
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TaskVector->Data = ProcessorBTestList->Data;
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//
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// Issue an IP interrupt to notify processor B that a task has
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// been scheduled for execution.
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//
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WRITE_REGISTER_ULONG(&DMA_CONTROL->IpInterruptRequest.Long,2);
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//
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// If timeout or Return Value indicates error, stop here.
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//
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if (((Timeout = WaitForIpInterrupt(5000)) == FALSE) || (TaskVector->ReturnValue == FALSE)) {
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if (!Timeout) {
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FwPrint("\r\n Wait for Processor B timeout occurred");
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} else {
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FwPrint("\r\n Processor B failed a test");
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}
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FwPrint(" Failed test = %08lx\r\n", (ULONG)ProcessorBTestList->Routine);
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//return FALSE;
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}
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//
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// Next test.
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//
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ProcessorBTestList++;
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}
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//
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// Now perform two CoherencyTest
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//
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FwPrint("\r\n Coherency Test.");
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ReturnValue = TRUE;
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//
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// Zero the page. Set the Task and notify processor B.
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// And execute the test simultaneously.
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//
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RtlZeroMemory((PVOID)EXCLUSIVE_PAGE_VIRTUAL_BASE,0x1000);
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FwFlushAllCaches();
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TaskVector->Routine = CoherencyTest;
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TaskVector->Data = (PVOID)EXCLUSIVE_PAGE_VIRTUAL_BASE;
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WRITE_REGISTER_ULONG(&DMA_CONTROL->IpInterruptRequest.Long,2);
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if (CoherencyTest((PVOID)EXCLUSIVE_PAGE_VIRTUAL_BASE) != 0) {
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FwPrint(" Processor A Failed.");
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ReturnValue = FALSE;
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} else {
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FwPrint("...");
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}
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//
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// Get and display results from B
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//
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WaitForIpInterrupt(1000);
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if (TaskVector->ReturnValue != 0) {
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FwPrint(" Processor B Failed.");
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ReturnValue = FALSE;
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} else {
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FwPrint("...");
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}
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//
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// Do the same with a shared page
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//
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RtlZeroMemory((PVOID)SHARED_PAGE_VIRTUAL_BASE,0x1000);
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FwFlushAllCaches();
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TaskVector->Routine = CoherencyTest;
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TaskVector->Data = (PVOID)SHARED_PAGE_VIRTUAL_BASE;
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WRITE_REGISTER_ULONG(&DMA_CONTROL->IpInterruptRequest.Long,2);
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if (CoherencyTest((PVOID)SHARED_PAGE_VIRTUAL_BASE) != 0) {
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FwPrint(" Processor A Failed.");
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ReturnValue = FALSE;
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} else {
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FwPrint("...");
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}
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WaitForIpInterrupt(1000);
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if (TaskVector->ReturnValue != 0) {
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FwPrint(" Processor B Failed.");
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ReturnValue = FALSE;
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} else {
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FwPrint("...");
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}
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//
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// Make processor B initialize its PCR
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//
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TaskVector->Routine = (PPROCESSOR_TASK_ROUTINE)InitializePCR;
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TaskVector->Data = 0;
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//
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// Issue an IP interrupt to notify processor B that a task has
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// been scheduled for execution.
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//
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WRITE_REGISTER_ULONG(&DMA_CONTROL->IpInterruptRequest.Long,2);
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//
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// If timeout or Return Value indicates error, stop here.
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//
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if (WaitForIpInterrupt(5000) == FALSE) {
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// FwPrint("\r\n Wait for Processor B timeout occurred in init PCR\r\n");
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return FALSE;
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}
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//
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// Make processor B cleanup it's caches.
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//
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TaskVector->Routine = (PPROCESSOR_TASK_ROUTINE)HalSweepDcache;
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TaskVector->Data = 0;
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//
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// Issue an IP interrupt to notify processor B that a task has
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// been scheduled for execution.
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//
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WRITE_REGISTER_ULONG(&DMA_CONTROL->IpInterruptRequest.Long,2);
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//
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// If timeout or Return Value indicates error, stop here.
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//
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if (WaitForIpInterrupt(5000) == FALSE) {
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// FwPrint("\r\n Wait for Processor B timeout occurred Hal sweep d cachew\r\n");
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return FALSE;
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}
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FwPrint(FW_OK_MSG);
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return ReturnValue;
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}
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#endif // DUO
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