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379 lines
10 KiB
379 lines
10 KiB
/*++
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Module Name:
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pci.h
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Abstract:
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This is the PCI bus specific header file used by device drivers.
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Author:
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Revision History:
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--*/
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#ifndef _PCI_
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#define _PCI_
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// begin_ntddk
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//
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// A PCI driver can read the complete 256 bytes of configuration
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// information for any PCI device by calling:
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//
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// ULONG
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// HalGetBusData (
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// IN BUS_DATA_TYPE PCIConfiguration,
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// IN ULONG PciBusNumber,
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// IN PCI_SLOT_NUMBER VirtualSlotNumber,
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// IN PPCI_COMMON_CONFIG &PCIDeviceConfig,
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// IN ULONG sizeof (PCIDeviceConfig)
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// );
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//
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// A return value of 0 means that the specified PCI bus does not exist.
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//
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// A return value of 2, with a VendorID of PCI_INVALID_VENDORID means
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// that the PCI bus does exist, but there is no device at the specified
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// VirtualSlotNumber (PCI Device/Function number).
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//
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//
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// begin_ntminiport
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typedef struct _PCI_SLOT_NUMBER {
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union {
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struct {
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ULONG DeviceNumber:5;
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ULONG FunctionNumber:3;
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ULONG Reserved:24;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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typedef struct _PCI_COMMON_CONFIG {
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USHORT VendorID; // (ro)
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USHORT DeviceID; // (ro)
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USHORT Command; // Device control
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USHORT Status;
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UCHAR RevisionID; // (ro)
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UCHAR ProgIf; // (ro)
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UCHAR SubClass; // (ro)
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UCHAR BaseClass; // (ro)
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UCHAR CacheLineSize; // (ro+)
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UCHAR LatencyTimer; // (ro+)
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UCHAR HeaderType; // (ro)
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UCHAR BIST; // Built in self test
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union {
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struct _PCI_HEADER_TYPE_0 {
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ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
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ULONG CIS;
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USHORT SubVendorID;
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USHORT SubSystemID;
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ULONG ROMBaseAddress;
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ULONG Reserved2[2];
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UCHAR InterruptLine; //
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UCHAR InterruptPin; // (ro)
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UCHAR MinimumGrant; // (ro)
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UCHAR MaximumLatency; // (ro)
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} type0;
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// end_ntddk end_ntminiport
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struct _PCI_HEADER_TYPE_1 {
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ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatency;
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UCHAR IOBase;
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UCHAR IOLimit;
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USHORT SecondaryStatus;
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USHORT MemoryBase;
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USHORT MemoryLimit;
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USHORT PrefetchBase;
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USHORT PrefetchLimit;
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ULONG PrefetchBaseUpper32;
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ULONG PrefetchLimitUpper32;
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USHORT IOBaseUpper16;
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USHORT IOLimitUpper16;
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ULONG Reserved;
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ULONG ROMBaseAddress;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type1;
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// begin_ntddk begin_ntminiport
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} u;
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UCHAR DeviceSpecific[192];
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_INVALID_VENDORID 0xFFFF
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//
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// Bit encodings for PCI_COMMON_CONFIG.HeaderType
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//
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#define PCI_MULTIFUNCTION 0x80
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#define PCI_DEVICE_TYPE 0x00
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#define PCI_BRIDGE_TYPE 0x01
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//
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// Bit encodings for PCI_COMMON_CONFIG.Command
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//
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#define PCI_ENABLE_IO_SPACE 0x0001
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#define PCI_ENABLE_MEMORY_SPACE 0x0002
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#define PCI_ENABLE_BUS_MASTER 0x0004
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#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
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#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
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#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
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#define PCI_ENABLE_PARITY 0x0040 // (ro+)
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#define PCI_ENABLE_WAIT_CYCLE 0x0080 // (ro+)
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#define PCI_ENABLE_SERR 0x0100 // (ro+)
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#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200 // (ro)
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//
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// Bit encodings for PCI_COMMON_CONFIG.Status
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//
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#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080 // (ro)
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#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
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#define PCI_STATUS_DEVSEL 0x0600 // 2 bits wide
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#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
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#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
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#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses
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//
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#define PCI_ADDRESS_IO_SPACE 0x00000001 // (ro)
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#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006 // (ro)
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#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008 // (ro)
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#define PCI_TYPE_32BIT 0
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#define PCI_TYPE_20BIT 2
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#define PCI_TYPE_64BIT 4
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses
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//
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#define PCI_ROMADDRESS_ENABLED 0x00000001
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//
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// Reference notes for PCI configuration fields:
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//
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// ro these field are read only. changes to these fields are ignored
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//
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// ro+ these field are intended to be read only and should be initialized
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// by the system to their proper values. However, driver may change
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// these settings.
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//
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// ---
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//
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// All resources comsumed by a PCI device start as unitialized
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// under NT. An uninitialized memory or I/O base address can be
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// determined by checking it's corrisponding enabled bit in the
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// PCI_COMMON_CONFIG.Command value. An InterruptLine is unitialized
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// if it contains the value of -1.
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//
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// end_ntminiport
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// end_ntddk
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//
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// PCI_REGISTRY_INFO - this structure is passed into the HAL from
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// the firmware. It signifies how many PCI bus(es) are present and
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// what style of access the PCI bus(es) support.
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//
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typedef struct _PCI_REGISTRY_INFO {
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UCHAR MajorRevision;
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UCHAR MinorRevision;
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UCHAR NoBuses;
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UCHAR HardwareMechanism;
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} PCI_REGISTRY_INFO, *PPCI_REGISTRY_INFO;
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//
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// PCI definitions for IOBase & IOLimit
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// PCIBridgeIO2Base(a,b) - convert IOBase & IOBaseUpper16 to ULONG IOBase
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// PCIBridgeIO2Limit(a,b) - convert IOLimit & IOLimitUpper6 to ULONG IOLimit
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//
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#define PciBridgeIO2Base(a,b) \
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( ((a >> 4) << 12) + (((a & 0xf) == 1) ? (b << 16) : 0) )
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#define PciBridgeIO2Limit(a,b) (PciBridgeIO2Base(a,b) | 0xfff)
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#define PciBridgeMemory2Base(a) (ULONG) ((a & 0xfff0) << 16)
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#define PciBridgeMemory2Limit(a) (PciBridgeMemory2Base(a) | 0xfffff)
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type1.BridgeControl
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//
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#define PCI_ENABLE_BRIDGE_PARITY_ERROR 0x0001
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#define PCI_ENABLE_BRIDGE_SERR 0x0002
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#define PCI_ENABLE_BRIDGE_ISA 0x0004
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#define PCI_ENABLE_BRIDGE_VGA 0x0008
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#define PCI_ENABLE_BRIDGE_MASTER_ABORT_SERR 0x0020
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#define PCI_ASSERT_BRIDGE_RESET 0x0040
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#define PCI_ENABLE_BRIDGE_FAST_BACK_TO_BACK 0x0080
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//
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// Definitions needed for Access to Hardware Type 1
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//
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#define PCI_TYPE1_ADDR_PORT ((PULONG) 0xCF8)
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#define PCI_TYPE1_DATA_PORT 0xCFC
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typedef struct _PCI_TYPE1_CFG_BITS {
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union {
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struct {
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Reserved2:7;
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ULONG Enable:1;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
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//
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// Definitions needed for Access to Hardware Type 2
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//
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#define PCI_TYPE2_CSE_PORT ((PUCHAR) 0xCF8)
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#define PCI_TYPE2_FORWARD_PORT ((PUCHAR) 0xCFA)
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#define PCI_TYPE2_ADDRESS_BASE 0xC
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typedef struct _PCI_TYPE2_CSE_BITS {
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union {
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struct {
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UCHAR Enable:1;
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UCHAR FunctionNumber:3;
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UCHAR Key:4;
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} bits;
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UCHAR AsUCHAR;
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} u;
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} PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
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typedef struct _PCI_TYPE2_ADDRESS_BITS {
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union {
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struct {
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USHORT RegisterNumber:8;
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USHORT Agent:4;
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USHORT AddressBase:4;
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} bits;
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USHORT AsUSHORT;
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} u;
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} PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
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//
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// Definitions for the config cycle format on the PCI bus.
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//
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typedef struct _PCI_TYPE0_CFG_CYCLE_BITS {
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union {
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struct {
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG Reserved2:21;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
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typedef struct _PCI_TYPE1_CFG_CYCLE_BITS {
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union {
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struct {
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Reserved2:8;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
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//
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// Portable portion of HAL & HAL bus extender definitions for BUSHANDLER
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// BusData for installed PCI buses.
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//
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typedef VOID
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(*PciPin2Line) (
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IN struct _BUS_HANDLER *BusHandler,
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IN struct _BUS_HANDLER *RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciData
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);
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typedef VOID
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(*PciLine2Pin) (
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IN struct _BUS_HANDLER *BusHandler,
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IN struct _BUS_HANDLER *RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciNewData,
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IN PPCI_COMMON_CONFIG PciOldData
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);
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typedef VOID
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(*PciReadWriteConfig) (
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IN struct _BUS_HANDLER *BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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#define PCI_DATA_TAG ' ICP'
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#define PCI_DATA_VERSION 1
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typedef struct _PCIBUSDATA {
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ULONG Tag;
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ULONG Version;
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PciReadWriteConfig ReadConfig;
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PciReadWriteConfig WriteConfig;
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PciPin2Line Pin2Line;
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PciLine2Pin Line2Pin;
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PCI_SLOT_NUMBER ParentSlot;
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PVOID Reserved[4];
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} PCIBUSDATA, *PPCIBUSDATA;
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#endif
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