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170 lines
3.2 KiB
170 lines
3.2 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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flush.c
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Abstract:
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This module implements i386 machine dependent kernel functions to flush
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the data and instruction caches and to stall processor execution.
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Author:
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David N. Cutler (davec) 26-Apr-1990
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "ki.h"
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// i386 and i486 have transparent caches, so these routines are nooped
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// out in macros in i386.h.
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#if 0
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VOID
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KeSweepDcache (
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IN BOOLEAN AllProcessors
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)
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/*++
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Routine Description:
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This function flushes the data cache on all processors that are currently
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running threads which are children of the current process or flushes the
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data cache on all processors in the host configuration.
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Arguments:
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AllProcessors - Supplies a boolean value that determines which data
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caches are flushed.
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Return Value:
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None.
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--*/
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{
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HalSweepDcache();
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return;
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}
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VOID
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KeSweepIcache (
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IN BOOLEAN AllProcessors
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)
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/*++
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Routine Description:
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This function flushes the instruction cache on all processors that are
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currently running threads which are children of the current process or
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flushes the instruction cache on all processors in the host configuration.
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Arguments:
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AllProcessors - Supplies a boolean value that determines which instruction
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caches are flushed.
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Return Value:
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None.
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--*/
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{
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HalSweepIcache();
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#if defined(R4000)
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HalSweepDcache();
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#endif
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return;
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}
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VOID
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KeSweepIcacheRange (
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function flushes the an range of virtual addresses from the primary
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instruction cache on all processors that are currently running threads
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which are children of the current process or flushes the range of virtual
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addresses from the primary instruction cache on all processors in the host
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configuration.
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Arguments:
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AllProcessors - Supplies a boolean value that determines which instruction
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caches are flushed.
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BaseAddress - Supplies a pointer to the base of the range that is flushed.
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Length - Supplies the length of the range that is flushed if the base
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address is specified.
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Return Value:
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None.
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--*/
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{
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ULONG Offset;
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//
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// If the length of the range is greater than the size of the primary
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// instruction cache, then set the length of the flush to the size of
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// the primary instruction cache and set the ase address of zero.
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//
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// N.B. It is assumed that the size of the primary instruction and
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// data caches are the same.
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//
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if (Length > PCR->FirstLevelIcacheSize) {
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BaseAddress = (PVOID)0;
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Length = PCR->FirstLevelIcacheSize;
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}
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//
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// Flush the specified range of virtual addresses from the primary
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// instruction cache.
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//
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Offset = (ULONG)BaseAddress & PCR->DcacheAlignment;
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Length = (Offset + Length + PCR->DcacheAlignment) & ~PCR->DcacheAlignment;
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BaseAddress = (PVOID)((ULONG)BaseAddress & ~PCR->DcacheAlignment);
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HalSweepIcacheRange(BaseAddress, Length);
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#if defined(R4000)
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HalSweepDcacheRange(BaseAddress, Length);
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#endif
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return;
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}
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#endif
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