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812 lines
26 KiB
812 lines
26 KiB
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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genoff.c
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Abstract:
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This module implements a program which generates structure offset
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definitions for kernel structures that are accessed in assembly code.
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Author:
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Bryan M. Willman (bryanwi) 16-Oct-90
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Revision History:
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--*/
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#include "ki.h"
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#pragma hdrstop
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#include "nturtl.h"
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#include "vdmntos.h"
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#include "abios.h"
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//
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// Define architecture specific generation macros.
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//
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#define genAlt(Name, Type, Member) \
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p2(#Name, OFFSET(Type, Member))
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#define genCom(Comment) \
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p1("\n"); \
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p1(";\n"); \
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p1("; " Comment "\n"); \
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p1(";\n"); \
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p1("\n")
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#define genDef(Prefix, Type, Member) \
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p2(#Prefix #Member, OFFSET(Type, Member))
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#define genVal(Name, Value) \
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p2(#Name, Value)
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#define genSpc() p1("\n");
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//
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// Define member offset computation macro.
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//
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#define OFFSET(type, field) ((LONG)(&((type *)0)->field))
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FILE *OutKs386;
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FILE *OutHal386;
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ULONG OutputEnabled;
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#define KS386 0x01
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#define HAL386 0x02
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#define KERNEL KS386
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#define HAL HAL386
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//
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// p1 prints a single string.
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//
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VOID p1(PUCHAR outstring);
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//
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// p2 prints the first argument as a string, followed by " equ " and
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// the hexadecimal value of "Value".
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//
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VOID p2(PUCHAR a, LONG b);
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//
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// p2a first argument is the format string. second argument is passed
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// to the printf function
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//
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VOID p2a(PUCHAR a, LONG b);
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//
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// EnableInc(a) - Enables output to goto specified include file
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//
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#define EnableInc(a) OutputEnabled |= a;
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//
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// DisableInc(a) - Disables output to goto specified include file
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//
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#define DisableInc(a) OutputEnabled &= ~a;
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int
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_CRTAPI1
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main(
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int argc,
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char *argv[]
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)
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{
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char *outName;
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printf ("Sizeof DeviceObject %d\n", sizeof (DEVICE_OBJECT));
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printf ("Sizeof DeviceObject Ext %d\n", sizeof (DEVOBJ_EXTENSION));
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outName = argc >= 2 ? argv[1] : "\\nt\\public\\sdk\\inc\\ks386.inc";
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OutKs386 = fopen(outName, "w" );
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if (OutKs386 == NULL) {
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fprintf(stderr, "GENi386: Could not create output file '%s'.\n", outName);
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fprintf( stderr, "sizeof( EPROCESS ) == %04x\n", sizeof( EPROCESS ) );
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fprintf( stderr, "Win32Process %08x\n",OFFSET(EPROCESS, Win32Process));
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exit (1);
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}
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fprintf( stderr, "GENi386: Writing %s header file.\n", outName );
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outName = argc >= 3 ? argv[2] : "\\nt\\private\\ntos\\inc\\hal386.inc";
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OutHal386 = fopen( outName, "w" );
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if (OutHal386 == NULL) {
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fprintf(stderr, "GENi386: Could not create output file '%s'.\n", outName);
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fprintf(stderr, "GENi386: Execution continuing. Hal results ignored '%s'.\n", outName);
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}
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fprintf( stderr, "GENi386: Writing %s header file.\n", outName );
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fprintf( stderr, "sizeof( TEB ) == %04x %s\n", sizeof( TEB ), sizeof( TEB ) >= PAGE_SIZE ? "Warning, TEB too Large" : "" );
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fprintf( stderr, "sizeof( PEB ) == %04x %s\n", sizeof( PEB ), sizeof( PEB ) >= PAGE_SIZE ? "Warning, PEB too Large" : "" );
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fprintf( stderr, "sizeof( KTHREAD ) == %04x\n", sizeof( KTHREAD ) );
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fprintf( stderr, "sizeof( ETHREAD ) == %04x\n", sizeof( ETHREAD ) );
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fprintf( stderr, "sizeof( KPROCESS ) == %04x\n", sizeof( KPROCESS ) );
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fprintf( stderr, "sizeof( EPROCESS ) == %04x\n", sizeof( EPROCESS ) );
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fprintf( stderr, "sizeof( KEVENT ) == %04x\n", sizeof( KEVENT ) );
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fprintf( stderr, "sizeof( KSEMAPHORE ) == %04x\n", sizeof( KSEMAPHORE ) );
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EnableInc (KS386);
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//
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// Include architecture independent definitions.
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//
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#include "..\genxx.inc"
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//
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// Generate architecture dependent definitions.
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//
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p1("\n");
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p1("; \n");
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p1("; Apc Record Structure Offset Definitions\n");
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p1("; \n");
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p1("\n");
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p2("ArNormalRoutine", OFFSET(KAPC_RECORD, NormalRoutine));
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p2("ArNormalContext", OFFSET(KAPC_RECORD, NormalContext));
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p2("ArSystemArgument1", OFFSET(KAPC_RECORD, SystemArgument1));
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p2("ArSystemArgument2", OFFSET(KAPC_RECORD, SystemArgument2));
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p2("ApcRecordLength", sizeof(KAPC_RECORD));
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p1("\n");
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EnableInc(HAL386);
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p1("\n");
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p1("; \n");
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p1("; Processor Control Registers Structure Offset Definitions\n");
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p1("; \n");
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p1("\n");
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p2("KI_BEGIN_KERNEL_RESERVED", KI_BEGIN_KERNEL_RESERVED);
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p1("ifdef NT_UP\n");
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p2a(" P0PCRADDRESS equ 0%lXH\n", KIP0PCRADDRESS);
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p2a(" PCR equ ds:[0%lXH]\n", KIP0PCRADDRESS);
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p1("else\n");
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p1(" PCR equ fs:\n");
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p1("endif\n\n");
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p2("PcExceptionList", OFFSET(KPCR, NtTib.ExceptionList));
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p2("PcInitialStack", OFFSET(KPCR, NtTib.StackBase));
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p2("PcStackLimit", OFFSET(KPCR, NtTib.StackLimit));
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p2("PcSelfPcr", OFFSET(KPCR, SelfPcr));
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p2("PcPrcb", OFFSET(KPCR, Prcb));
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p2("PcTeb", OFFSET(KPCR, NtTib.Self));
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p2("PcIrql", OFFSET(KPCR, Irql));
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p2("PcIRR", OFFSET(KPCR, IRR));
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p2("PcIrrActive", OFFSET(KPCR, IrrActive));
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p2("PcIDR", OFFSET(KPCR, IDR));
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p2("PcIdt", OFFSET(KPCR, IDT));
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p2("PcGdt", OFFSET(KPCR, GDT));
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p2("PcTss", OFFSET(KPCR, TSS));
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p2("PcDebugActive", OFFSET(KPCR, DebugActive));
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p2("PcNumber", OFFSET(KPCR, Number));
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p2("PcVdmAlert", OFFSET(KPCR, VdmAlert));
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p2("PcSetMember", OFFSET(KPCR, SetMember));
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p2("PcStallScaleFactor", OFFSET(KPCR, StallScaleFactor));
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p2("PcHal", OFFSET(KPCR, HalReserved));
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p2("PcKernel", OFFSET(KPCR, KernelReserved));
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DisableInc (HAL386);
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p2("PcPrcbData", OFFSET(KPCR, PrcbData));
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p2("ProcessorControlRegisterLength", sizeof(KPCR));
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p2("TebPeb", OFFSET(TEB, ProcessEnvironmentBlock));
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p2("PebBeingDebugged", OFFSET(PEB, BeingDebugged));
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p2("PebKernelCallbackTable", OFFSET(PEB, KernelCallbackTable));
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EnableInc (HAL386);
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p1("\n");
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p1(";\n");
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p1("; Defines for user shared data\n");
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p1(";\n");
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p2("USER_SHARED_DATA", KI_USER_SHARED_DATA);
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p2("MM_SHARED_USER_DATA_VA", MM_SHARED_USER_DATA_VA);
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p2a("USERDATA equ ds:[0%lXH]\n", KI_USER_SHARED_DATA);
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p2("UsTickCountLow", OFFSET(KUSER_SHARED_DATA, TickCountLow));
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p2("UsTickCountMultiplier", OFFSET(KUSER_SHARED_DATA, TickCountMultiplier));
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p2("UsInterruptTime", OFFSET(KUSER_SHARED_DATA, InterruptTime));
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p2("UsSystemTime", OFFSET(KUSER_SHARED_DATA, SystemTime));
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p1("\n");
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p1(";\n");
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p1("; Tss Structure Offset Definitions\n");
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p1(";\n\n");
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p2("TssEsp0", OFFSET(KTSS, Esp0));
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p2("TssCR3", OFFSET(KTSS, CR3));
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p2("TssIoMapBase", OFFSET(KTSS, IoMapBase));
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p2("TssIoMaps", OFFSET(KTSS, IoMaps));
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p2("TssLength", sizeof(KTSS));
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p1("\n");
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DisableInc (HAL386);
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EnableInc (HAL386);
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p1(";\n");
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p1("; Gdt Descriptor Offset Definitions\n");
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p1(";\n\n");
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p2("KGDT_R3_DATA", KGDT_R3_DATA);
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p2("KGDT_R3_CODE", KGDT_R3_CODE);
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p2("KGDT_R0_CODE", KGDT_R0_CODE);
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p2("KGDT_R0_DATA", KGDT_R0_DATA);
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p2("KGDT_R0_PCR", KGDT_R0_PCR);
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p2("KGDT_STACK16", KGDT_STACK16);
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p2("KGDT_CODE16", KGDT_CODE16);
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p2("KGDT_TSS", KGDT_TSS);
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DisableInc (HAL386);
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p2("KGDT_R3_TEB", KGDT_R3_TEB);
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p2("KGDT_DF_TSS", KGDT_DF_TSS);
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p2("KGDT_NMI_TSS", KGDT_NMI_TSS);
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p2("KGDT_LDT", KGDT_LDT);
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p1("\n");
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EnableInc (HAL386);
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p1(";\n");
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p1("; GdtEntry Offset Definitions\n");
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p1(";\n\n");
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p2("KgdtBaseLow", OFFSET(KGDTENTRY, BaseLow));
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p2("KgdtBaseMid", OFFSET(KGDTENTRY, HighWord.Bytes.BaseMid));
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p2("KgdtBaseHi", OFFSET(KGDTENTRY, HighWord.Bytes.BaseHi));
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p2("KgdtLimitHi", OFFSET(KGDTENTRY, HighWord.Bytes.Flags2));
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p2("KgdtLimitLow", OFFSET(KGDTENTRY, LimitLow));
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p1("\n");
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//
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// Processor block structure definitions.
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//
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genCom("Processor Block Structure Offset Definitions");
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genDef(Pb, KPRCB, CurrentThread);
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genDef(Pb, KPRCB, NextThread);
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genDef(Pb, KPRCB, IdleThread);
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genDef(Pb, KPRCB, Number);
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genDef(Pb, KPRCB, SetMember);
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genDef(Pb, KPRCB, CpuID);
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genDef(Pb, KPRCB, CpuType);
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genDef(Pb, KPRCB, CpuStep);
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genDef(Pb, KPRCB, HalReserved);
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genDef(Pb, KPRCB, ProcessorState);
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DisableInc (HAL386);
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genDef(Pb, KPRCB, NpxThread);
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genDef(Pb, KPRCB, InterruptCount);
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genDef(Pb, KPRCB, KernelTime);
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genDef(Pb, KPRCB, UserTime);
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genDef(Pb, KPRCB, DpcTime);
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genDef(Pb, KPRCB, InterruptTime);
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genDef(Pb, KPRCB, ApcBypassCount);
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genDef(Pb, KPRCB, DpcBypassCount);
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genDef(Pb, KPRCB, AdjustDpcThreshold);
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genDef(Pb, KPRCB, ThreadStartCount);
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genAlt(PbAlignmentFixupCount, KPRCB, KeAlignmentFixupCount);
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genAlt(PbContextSwitches, KPRCB, KeContextSwitches);
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genAlt(PbDcacheFlushCount, KPRCB, KeDcacheFlushCount);
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genAlt(PbExceptionDispatchCount, KPRCB, KeExceptionDispatchCount);
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genAlt(PbFirstLevelTbFills, KPRCB, KeFirstLevelTbFills);
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genAlt(PbFloatingEmulationCount, KPRCB, KeFloatingEmulationCount);
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genAlt(PbIcacheFlushCount, KPRCB, KeIcacheFlushCount);
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genAlt(PbSecondLevelTbFills, KPRCB, KeSecondLevelTbFills);
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genAlt(PbSystemCalls, KPRCB, KeSystemCalls);
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genDef(Pb, KPRCB, CurrentPacket);
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genDef(Pb, KPRCB, TargetSet);
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genDef(Pb, KPRCB, WorkerRoutine);
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genDef(Pb, KPRCB, IpiFrozen);
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genDef(Pb, KPRCB, RequestSummary);
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genDef(Pb, KPRCB, SignalDone);
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genDef(Pb, KPRCB, IpiFrame);
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genDef(Pb, KPRCB, DpcInterruptRequested);
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genDef(Pb, KPRCB, MaximumDpcQueueDepth);
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genDef(Pb, KPRCB, MinimumDpcRate);
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genDef(Pb, KPRCB, DpcListHead);
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genDef(Pb, KPRCB, DpcQueueDepth);
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genDef(Pb, KPRCB, DpcRoutineActive);
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genDef(Pb, KPRCB, DpcCount);
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genDef(Pb, KPRCB, DpcLastCount);
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genDef(Pb, KPRCB, DpcRequestRate);
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genDef(Pb, KPRCB, DpcLock);
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genDef(Pb, KPRCB, SkipTick);
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genDef(Pb, KPRCB, QuantumEnd);
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genVal(ProcessorBlockLength, ((sizeof(KPRCB) + 15) & ~15));
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//
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// Interprocessor command definitions.
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//
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genCom("Immediate Interprocessor Command Definitions");
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genVal(IPI_APC, IPI_APC);
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genVal(IPI_DPC, IPI_DPC);
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genVal(IPI_FREEZE, IPI_FREEZE);
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genVal(IPI_PACKET_READY, IPI_PACKET_READY);
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p1("; \n");
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p1("; Thread Environment Block Structure Offset Definitions\n");
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p1("; \n");
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p1("\n");
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p2("TbExceptionList", OFFSET(TEB, NtTib.ExceptionList));
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p2("TbStackBase", OFFSET(TEB, NtTib.StackBase));
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p2("TbStackLimit", OFFSET(TEB, NtTib.StackLimit));
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p2("TbEnvironmentPointer", OFFSET(TEB, EnvironmentPointer));
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p2("TbVersion", OFFSET(TEB, NtTib.Version));
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p2("TbFiberData", OFFSET(TEB, NtTib.FiberData));
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p2("TbArbitraryUserPointer", OFFSET(TEB, NtTib.ArbitraryUserPointer));
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p2("TbClientId", OFFSET(TEB, ClientId));
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p2("TbThreadLocalStoragePointer", OFFSET(TEB,
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ThreadLocalStoragePointer));
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p2("TbCountOfOwnedCriticalSections", OFFSET(TEB, CountOfOwnedCriticalSections));
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p2("TbSystemReserved1", OFFSET(TEB, SystemReserved1));
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p2("TbSystemReserved2", OFFSET(TEB, SystemReserved2));
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p2("TbVdm", OFFSET(TEB, Vdm));
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p2("TbCsrClientThread", OFFSET(TEB, CsrClientThread));
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p2("TbGdiClientPID", OFFSET(TEB, GdiClientPID));
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p2("TbGdiClientTID", OFFSET(TEB, GdiClientTID));
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p2("TbGdiThreadLocalInfo", OFFSET(TEB, GdiThreadLocalInfo));
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p2("TbglDispatchTable", OFFSET(TEB, glDispatchTable));
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p2("TbglSectionInfo", OFFSET(TEB, glSectionInfo));
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p2("TbglSection", OFFSET(TEB, glSection));
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p2("TbglTable", OFFSET(TEB, glTable));
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p2("TbglCurrentRC", OFFSET(TEB, glCurrentRC));
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p2("TbglContext", OFFSET(TEB, glContext));
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p2("TbWin32ClientInfo", OFFSET(TEB, Win32ClientInfo));
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p2("TbWOW32Reserved", OFFSET(TEB, WOW32Reserved));
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p2("TbWin32ThreadInfo", OFFSET(TEB, Win32ThreadInfo));
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p2("TbSpare1", OFFSET(TEB, Spare1));
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p2("TbExceptionCode", OFFSET(TEB, ExceptionCode));
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p2("TbDeallocationStack", OFFSET(TEB, DeallocationStack));
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p2("TbGdiBatchCount", OFFSET(TEB, GdiBatchCount));
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EnableInc (HAL386);
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p1(";\n");
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p1(";\n");
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p1("; Time Fields (TIME_FIELDS) Structure Offset Definitions\n");
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p1(";\n\n");
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p2("TfSecond", OFFSET(TIME_FIELDS, Second));
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p2("TfMinute", OFFSET(TIME_FIELDS, Minute));
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p2("TfHour", OFFSET(TIME_FIELDS, Hour));
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p2("TfWeekday", OFFSET(TIME_FIELDS, Weekday));
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p2("TfDay", OFFSET(TIME_FIELDS, Day));
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p2("TfMonth", OFFSET(TIME_FIELDS, Month));
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p2("TfYear", OFFSET(TIME_FIELDS, Year));
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p2("TfMilliseconds", OFFSET(TIME_FIELDS, Milliseconds));
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p1("\n");
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DisableInc (HAL386);
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EnableInc (HAL386);
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p1("; \n");
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p1("; constants for system irql and IDT vector conversion\n");
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p1("; \n");
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p1("\n");
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p2("MAXIMUM_IDTVECTOR", MAXIMUM_IDTVECTOR);
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p2("MAXIMUM_PRIMARY_VECTOR", MAXIMUM_PRIMARY_VECTOR);
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p2("PRIMARY_VECTOR_BASE", PRIMARY_VECTOR_BASE);
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p2("RPL_MASK", RPL_MASK);
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p2("MODE_MASK", MODE_MASK);
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p1("\n");
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p1("; \n");
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p1("; Flags in the CR0 register\n");
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p1("; \n");
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p1("\n");
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p2("CR0_PG", CR0_PG);
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p2("CR0_ET", CR0_ET);
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p2("CR0_TS", CR0_TS);
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p2("CR0_EM", CR0_EM);
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p2("CR0_MP", CR0_MP);
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p2("CR0_PE", CR0_PE);
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p2("CR0_CD", CR0_CD);
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p2("CR0_NW", CR0_NW);
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p2("CR0_AM", CR0_AM);
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p2("CR0_WP", CR0_WP);
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p2("CR0_NE", CR0_NE);
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p1("\n");
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p1("; \n");
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p1("; Flags in the CR4 register\n");
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p1("; \n");
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p1("\n");
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p2("CR4_VME", CR4_VME);
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p2("CR4_PVI", CR4_PVI);
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p2("CR4_TSD", CR4_TSD);
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p2("CR4_DE", CR4_DE);
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p2("CR4_PSE", CR4_PSE);
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p2("CR4_PAE", CR4_PAE);
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p2("CR4_MCE", CR4_MCE);
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p2("CR4_PGE", CR4_PGE);
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p1("; \n");
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p1("; Miscellaneous Definitions\n");
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p1("; \n");
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p1("\n");
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p2("MAXIMUM_PROCESSORS", MAXIMUM_PROCESSORS);
|
|
p2("INITIAL_STALL_COUNT", INITIAL_STALL_COUNT);
|
|
p2("IRQL_NOT_GREATER_OR_EQUAL", IRQL_NOT_GREATER_OR_EQUAL);
|
|
p2("IRQL_NOT_LESS_OR_EQUAL", IRQL_NOT_LESS_OR_EQUAL);
|
|
DisableInc (HAL386);
|
|
p2("BASE_PRIORITY_THRESHOLD", BASE_PRIORITY_THRESHOLD);
|
|
p2("EVENT_PAIR_INCREMENT", EVENT_PAIR_INCREMENT);
|
|
p2("LOW_REALTIME_PRIORITY", LOW_REALTIME_PRIORITY);
|
|
p2("BlackHole", 0xffffa000);
|
|
p2("KERNEL_LARGE_STACK_COMMIT", KERNEL_LARGE_STACK_COMMIT);
|
|
p2("KERNEL_STACK_SIZE", KERNEL_STACK_SIZE);
|
|
p2("DOUBLE_FAULT_STACK_SIZE", DOUBLE_FAULT_STACK_SIZE);
|
|
p2("EFLAG_SELECT", EFLAG_SELECT);
|
|
p2("BREAKPOINT_BREAK ", BREAKPOINT_BREAK);
|
|
p2("IPI_FREEZE", IPI_FREEZE);
|
|
p2("CLOCK_QUANTUM_DECREMENT", CLOCK_QUANTUM_DECREMENT);
|
|
p2("READY_SKIP_QUANTUM", READY_SKIP_QUANTUM);
|
|
p2("THREAD_QUANTUM", THREAD_QUANTUM);
|
|
p2("WAIT_QUANTUM_DECREMENT", WAIT_QUANTUM_DECREMENT);
|
|
p2("ROUND_TRIP_DECREMENT_COUNT", ROUND_TRIP_DECREMENT_COUNT);
|
|
|
|
//
|
|
// Print trap frame offsets relative to sp.
|
|
//
|
|
|
|
EnableInc (HAL386);
|
|
p1("\n");
|
|
p1("; \n");
|
|
p1("; Trap Frame Offset Definitions and Length\n");
|
|
p1("; \n");
|
|
p1("\n");
|
|
|
|
p2("TsExceptionList", OFFSET(KTRAP_FRAME, ExceptionList));
|
|
p2("TsPreviousPreviousMode", OFFSET(KTRAP_FRAME, PreviousPreviousMode));
|
|
p2("TsSegGs", OFFSET(KTRAP_FRAME, SegGs));
|
|
p2("TsSegFs", OFFSET(KTRAP_FRAME, SegFs));
|
|
p2("TsSegEs", OFFSET(KTRAP_FRAME, SegEs));
|
|
p2("TsSegDs", OFFSET(KTRAP_FRAME, SegDs));
|
|
p2("TsEdi", OFFSET(KTRAP_FRAME, Edi));
|
|
p2("TsEsi", OFFSET(KTRAP_FRAME, Esi));
|
|
p2("TsEbp", OFFSET(KTRAP_FRAME, Ebp));
|
|
p2("TsEbx", OFFSET(KTRAP_FRAME, Ebx));
|
|
p2("TsEdx", OFFSET(KTRAP_FRAME, Edx));
|
|
p2("TsEcx", OFFSET(KTRAP_FRAME, Ecx));
|
|
p2("TsEax", OFFSET(KTRAP_FRAME, Eax));
|
|
p2("TsErrCode", OFFSET(KTRAP_FRAME, ErrCode));
|
|
p2("TsEip", OFFSET(KTRAP_FRAME, Eip));
|
|
p2("TsSegCs", OFFSET(KTRAP_FRAME, SegCs));
|
|
p2("TsEflags", OFFSET(KTRAP_FRAME, EFlags));
|
|
p2("TsHardwareEsp", OFFSET(KTRAP_FRAME, HardwareEsp));
|
|
p2("TsHardwareSegSs", OFFSET(KTRAP_FRAME, HardwareSegSs));
|
|
p2("TsTempSegCs", OFFSET(KTRAP_FRAME, TempSegCs));
|
|
p2("TsTempEsp", OFFSET(KTRAP_FRAME, TempEsp));
|
|
p2("TsDbgEbp", OFFSET(KTRAP_FRAME, DbgEbp));
|
|
p2("TsDbgEip", OFFSET(KTRAP_FRAME, DbgEip));
|
|
p2("TsDbgArgMark", OFFSET(KTRAP_FRAME, DbgArgMark));
|
|
p2("TsDbgArgPointer", OFFSET(KTRAP_FRAME, DbgArgPointer));
|
|
p2("TsDr0", OFFSET(KTRAP_FRAME, Dr0));
|
|
p2("TsDr1", OFFSET(KTRAP_FRAME, Dr1));
|
|
p2("TsDr2", OFFSET(KTRAP_FRAME, Dr2));
|
|
p2("TsDr3", OFFSET(KTRAP_FRAME, Dr3));
|
|
p2("TsDr6", OFFSET(KTRAP_FRAME, Dr6));
|
|
p2("TsDr7", OFFSET(KTRAP_FRAME, Dr7));
|
|
p2("TsV86Es", OFFSET(KTRAP_FRAME, V86Es));
|
|
p2("TsV86Ds", OFFSET(KTRAP_FRAME, V86Ds));
|
|
p2("TsV86Fs", OFFSET(KTRAP_FRAME, V86Fs));
|
|
p2("TsV86Gs", OFFSET(KTRAP_FRAME, V86Gs));
|
|
p2("KTRAP_FRAME_LENGTH", KTRAP_FRAME_LENGTH);
|
|
p2("KTRAP_FRAME_ALIGN", KTRAP_FRAME_ALIGN);
|
|
p2("FRAME_EDITED", FRAME_EDITED);
|
|
p2("EFLAGS_ALIGN_CHECK", EFLAGS_ALIGN_CHECK);
|
|
p2("EFLAGS_V86_MASK", EFLAGS_V86_MASK);
|
|
p2("EFLAGS_INTERRUPT_MASK", EFLAGS_INTERRUPT_MASK);
|
|
p2("EFLAGS_VIF", EFLAGS_VIF);
|
|
p2("EFLAGS_VIP", EFLAGS_VIP);
|
|
p2("EFLAGS_USER_SANITIZE", EFLAGS_USER_SANITIZE);
|
|
p1("\n");
|
|
|
|
|
|
p1(";\n");
|
|
p1("; Context Frame Offset and Flag Definitions\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("CONTEXT_FULL", CONTEXT_FULL);
|
|
p2("CONTEXT_DEBUG_REGISTERS", CONTEXT_DEBUG_REGISTERS);
|
|
p2("CONTEXT_CONTROL", CONTEXT_CONTROL);
|
|
p2("CONTEXT_FLOATING_POINT", CONTEXT_FLOATING_POINT);
|
|
p2("CONTEXT_INTEGER", CONTEXT_INTEGER);
|
|
p2("CONTEXT_SEGMENTS", CONTEXT_SEGMENTS);
|
|
p1("\n");
|
|
|
|
//
|
|
// Print context frame offsets relative to sp.
|
|
//
|
|
|
|
p2("CsContextFlags", OFFSET(CONTEXT, ContextFlags));
|
|
p2("CsFloatSave", OFFSET(CONTEXT, FloatSave));
|
|
p2("CsSegGs", OFFSET(CONTEXT, SegGs));
|
|
p2("CsSegFs", OFFSET(CONTEXT, SegFs));
|
|
p2("CsSegEs", OFFSET(CONTEXT, SegEs));
|
|
p2("CsSegDs", OFFSET(CONTEXT, SegDs));
|
|
p2("CsEdi", OFFSET(CONTEXT, Edi));
|
|
p2("CsEsi", OFFSET(CONTEXT, Esi));
|
|
p2("CsEbp", OFFSET(CONTEXT, Ebp));
|
|
p2("CsEbx", OFFSET(CONTEXT, Ebx));
|
|
p2("CsEdx", OFFSET(CONTEXT, Edx));
|
|
p2("CsEcx", OFFSET(CONTEXT, Ecx));
|
|
p2("CsEax", OFFSET(CONTEXT, Eax));
|
|
p2("CsEip", OFFSET(CONTEXT, Eip));
|
|
p2("CsSegCs", OFFSET(CONTEXT, SegCs));
|
|
p2("CsEflags", OFFSET(CONTEXT, EFlags));
|
|
p2("CsEsp", OFFSET(CONTEXT, Esp));
|
|
p2("CsSegSs", OFFSET(CONTEXT, SegSs));
|
|
p2("CsDr0", OFFSET(CONTEXT, Dr0));
|
|
p2("CsDr1", OFFSET(CONTEXT, Dr1));
|
|
p2("CsDr2", OFFSET(CONTEXT, Dr2));
|
|
p2("CsDr3", OFFSET(CONTEXT, Dr3));
|
|
p2("CsDr6", OFFSET(CONTEXT, Dr6));
|
|
p2("CsDr7", OFFSET(CONTEXT, Dr7));
|
|
p2("ContextFrameLength", (sizeof(CONTEXT) + 15) & (~15));
|
|
p2("DR6_LEGAL", DR6_LEGAL);
|
|
p2("DR7_LEGAL", DR7_LEGAL);
|
|
p2("DR7_ACTIVE", DR7_ACTIVE);
|
|
|
|
//
|
|
// Print Registration Record Offsets relative to base
|
|
//
|
|
|
|
p2("ErrHandler",
|
|
OFFSET(EXCEPTION_REGISTRATION_RECORD, Handler));
|
|
p2("ErrNext",
|
|
OFFSET(EXCEPTION_REGISTRATION_RECORD, Next));
|
|
p1("\n");
|
|
|
|
//
|
|
// Print floating point field offsets relative to Context.FloatSave
|
|
//
|
|
|
|
p1(";\n");
|
|
p1("; Floating save area field offset definitions\n");
|
|
p1(";\n");
|
|
p2("FpControlWord ", OFFSET(FLOATING_SAVE_AREA, ControlWord));
|
|
p2("FpStatusWord ", OFFSET(FLOATING_SAVE_AREA, StatusWord));
|
|
p2("FpTagWord ", OFFSET(FLOATING_SAVE_AREA, TagWord));
|
|
p2("FpErrorOffset ", OFFSET(FLOATING_SAVE_AREA, ErrorOffset));
|
|
p2("FpErrorSelector", OFFSET(FLOATING_SAVE_AREA, ErrorSelector));
|
|
p2("FpDataOffset ", OFFSET(FLOATING_SAVE_AREA, DataOffset));
|
|
p2("FpDataSelector ", OFFSET(FLOATING_SAVE_AREA, DataSelector));
|
|
p2("FpRegisterArea ", OFFSET(FLOATING_SAVE_AREA, RegisterArea));
|
|
p2("FpCr0NpxState ", OFFSET(FLOATING_SAVE_AREA, Cr0NpxState));
|
|
|
|
p1("\n");
|
|
p2("NPX_FRAME_LENGTH", sizeof(FLOATING_SAVE_AREA));
|
|
|
|
//
|
|
// Processor State Frame offsets relative to base
|
|
//
|
|
|
|
p1(";\n");
|
|
p1("; Processor State Frame Offset Definitions\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("PsContextFrame",
|
|
OFFSET(KPROCESSOR_STATE, ContextFrame));
|
|
p2("PsSpecialRegisters",
|
|
OFFSET(KPROCESSOR_STATE, SpecialRegisters));
|
|
p2("SrCr0", OFFSET(KSPECIAL_REGISTERS, Cr0));
|
|
p2("SrCr2", OFFSET(KSPECIAL_REGISTERS, Cr2));
|
|
p2("SrCr3", OFFSET(KSPECIAL_REGISTERS, Cr3));
|
|
p2("SrCr4", OFFSET(KSPECIAL_REGISTERS, Cr4));
|
|
p2("SrKernelDr0", OFFSET(KSPECIAL_REGISTERS, KernelDr0));
|
|
p2("SrKernelDr1", OFFSET(KSPECIAL_REGISTERS, KernelDr1));
|
|
p2("SrKernelDr2", OFFSET(KSPECIAL_REGISTERS, KernelDr2));
|
|
p2("SrKernelDr3", OFFSET(KSPECIAL_REGISTERS, KernelDr3));
|
|
p2("SrKernelDr6", OFFSET(KSPECIAL_REGISTERS, KernelDr6));
|
|
p2("SrKernelDr7", OFFSET(KSPECIAL_REGISTERS, KernelDr7));
|
|
p2("SrGdtr", OFFSET(KSPECIAL_REGISTERS, Gdtr.Limit));
|
|
|
|
p2("SrIdtr", OFFSET(KSPECIAL_REGISTERS, Idtr.Limit));
|
|
p2("SrTr", OFFSET(KSPECIAL_REGISTERS, Tr));
|
|
p2("SrLdtr", OFFSET(KSPECIAL_REGISTERS, Ldtr));
|
|
p2("ProcessorStateLength", ((sizeof(KPROCESSOR_STATE) + 15) & ~15));
|
|
DisableInc (HAL386);
|
|
|
|
//
|
|
// E Process fields relative to base
|
|
//
|
|
|
|
p1(";\n");
|
|
p1("; EPROCESS\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("EpDebugPort",
|
|
OFFSET(EPROCESS, DebugPort));
|
|
|
|
//
|
|
// E Resource fields relative to base
|
|
//
|
|
|
|
p1("\n");
|
|
p1(";\n");
|
|
p1("; NTDDK Resource\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("RsOwnerThreads", OFFSET(NTDDK_ERESOURCE, OwnerThreads));
|
|
p2("RsOwnerCounts", OFFSET(NTDDK_ERESOURCE, OwnerCounts));
|
|
p2("RsTableSize", OFFSET(NTDDK_ERESOURCE, TableSize));
|
|
p2("RsActiveCount", OFFSET(NTDDK_ERESOURCE, ActiveCount));
|
|
p2("RsFlag", OFFSET(NTDDK_ERESOURCE, Flag));
|
|
p2("RsInitialOwnerThreads", OFFSET(NTDDK_ERESOURCE, InitialOwnerThreads));
|
|
p2("RsOwnedExclusive", ResourceOwnedExclusive);
|
|
|
|
//
|
|
// Define machine type (temporarily)
|
|
//
|
|
|
|
EnableInc (HAL386);
|
|
p1(";\n");
|
|
p1("; Machine type definitions (Temporarily)\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("MACHINE_TYPE_ISA", MACHINE_TYPE_ISA);
|
|
p2("MACHINE_TYPE_EISA", MACHINE_TYPE_EISA);
|
|
p2("MACHINE_TYPE_MCA", MACHINE_TYPE_MCA);
|
|
|
|
DisableInc (HAL386);
|
|
p1(";\n");
|
|
p1("; KeFeatureBits defines\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("KF_V86_VIS", KF_V86_VIS);
|
|
p2("KF_RDTSC", KF_RDTSC);
|
|
p2("KF_CR4", KF_CR4);
|
|
p2("KF_GLOBAL_PAGE", KF_GLOBAL_PAGE);
|
|
p2("KF_LARGE_PAGE", KF_LARGE_PAGE);
|
|
p2("KF_CMPXCHG8B", KF_CMPXCHG8B);
|
|
|
|
EnableInc (HAL386);
|
|
p1(";\n");
|
|
p1("; LoaderParameterBlock offsets relative to base\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("LpbLoadOrderListHead",OFFSET(LOADER_PARAMETER_BLOCK,LoadOrderListHead));
|
|
p2("LpbMemoryDescriptorListHead",OFFSET(LOADER_PARAMETER_BLOCK,MemoryDescriptorListHead));
|
|
p2("LpbKernelStack",OFFSET(LOADER_PARAMETER_BLOCK,KernelStack));
|
|
p2("LpbPrcb",OFFSET(LOADER_PARAMETER_BLOCK,Prcb));
|
|
p2("LpbProcess",OFFSET(LOADER_PARAMETER_BLOCK,Process));
|
|
p2("LpbThread",OFFSET(LOADER_PARAMETER_BLOCK,Thread));
|
|
p2("LpbI386",OFFSET(LOADER_PARAMETER_BLOCK,u.I386));
|
|
p2("LpbRegistryLength",OFFSET(LOADER_PARAMETER_BLOCK,RegistryLength));
|
|
p2("LpbRegistryBase",OFFSET(LOADER_PARAMETER_BLOCK,RegistryBase));
|
|
p2("LpbConfigurationRoot",OFFSET(LOADER_PARAMETER_BLOCK,ConfigurationRoot));
|
|
p2("LpbArcBootDeviceName",OFFSET(LOADER_PARAMETER_BLOCK,ArcBootDeviceName));
|
|
p2("LpbArcHalDeviceName",OFFSET(LOADER_PARAMETER_BLOCK,ArcHalDeviceName));
|
|
DisableInc (HAL386);
|
|
|
|
p2("PAGE_SIZE",PAGE_SIZE);
|
|
|
|
//
|
|
// Define the VDM instruction emulation count indexes
|
|
//
|
|
|
|
p1("\n");
|
|
p1(";\n");
|
|
p1("; VDM equates.\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("VDM_INDEX_Invalid", VDM_INDEX_Invalid);
|
|
p2("VDM_INDEX_0F", VDM_INDEX_0F);
|
|
p2("VDM_INDEX_ESPrefix", VDM_INDEX_ESPrefix);
|
|
p2("VDM_INDEX_CSPrefix", VDM_INDEX_CSPrefix);
|
|
p2("VDM_INDEX_SSPrefix", VDM_INDEX_SSPrefix);
|
|
p2("VDM_INDEX_DSPrefix", VDM_INDEX_DSPrefix);
|
|
p2("VDM_INDEX_FSPrefix", VDM_INDEX_FSPrefix);
|
|
p2("VDM_INDEX_GSPrefix", VDM_INDEX_GSPrefix);
|
|
p2("VDM_INDEX_OPER32Prefix", VDM_INDEX_OPER32Prefix);
|
|
p2("VDM_INDEX_ADDR32Prefix", VDM_INDEX_ADDR32Prefix);
|
|
p2("VDM_INDEX_INSB", VDM_INDEX_INSB);
|
|
p2("VDM_INDEX_INSW", VDM_INDEX_INSW);
|
|
p2("VDM_INDEX_OUTSB", VDM_INDEX_OUTSB);
|
|
p2("VDM_INDEX_OUTSW", VDM_INDEX_OUTSW);
|
|
p2("VDM_INDEX_PUSHF", VDM_INDEX_PUSHF);
|
|
p2("VDM_INDEX_POPF", VDM_INDEX_POPF);
|
|
p2("VDM_INDEX_INTnn", VDM_INDEX_INTnn);
|
|
p2("VDM_INDEX_INTO", VDM_INDEX_INTO);
|
|
p2("VDM_INDEX_IRET", VDM_INDEX_IRET);
|
|
p2("VDM_INDEX_NPX", VDM_INDEX_NPX);
|
|
p2("VDM_INDEX_INBimm", VDM_INDEX_INBimm);
|
|
p2("VDM_INDEX_INWimm", VDM_INDEX_INWimm);
|
|
p2("VDM_INDEX_OUTBimm", VDM_INDEX_OUTBimm);
|
|
p2("VDM_INDEX_OUTWimm", VDM_INDEX_OUTWimm);
|
|
p2("VDM_INDEX_INB", VDM_INDEX_INB);
|
|
p2("VDM_INDEX_INW", VDM_INDEX_INW);
|
|
p2("VDM_INDEX_OUTB", VDM_INDEX_OUTB);
|
|
p2("VDM_INDEX_OUTW", VDM_INDEX_OUTW);
|
|
p2("VDM_INDEX_LOCKPrefix", VDM_INDEX_LOCKPrefix);
|
|
p2("VDM_INDEX_REPNEPrefix", VDM_INDEX_REPNEPrefix);
|
|
p2("VDM_INDEX_REPPrefix", VDM_INDEX_REPPrefix);
|
|
p2("VDM_INDEX_CLI", VDM_INDEX_CLI);
|
|
p2("VDM_INDEX_STI", VDM_INDEX_STI);
|
|
p2("VDM_INDEX_HLT", VDM_INDEX_HLT);
|
|
p2("MAX_VDM_INDEX", MAX_VDM_INDEX);
|
|
|
|
//
|
|
// Vdm feature bits
|
|
//
|
|
|
|
p1("\n");
|
|
p1(";\n");
|
|
p1("; VDM feature bits.\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("V86_VIRTUAL_INT_EXTENSIONS",V86_VIRTUAL_INT_EXTENSIONS);
|
|
p2("PM_VIRTUAL_INT_EXTENSIONS",PM_VIRTUAL_INT_EXTENSIONS);
|
|
|
|
//
|
|
// Selector type
|
|
//
|
|
p1("\n");
|
|
p1(";\n");
|
|
p1("; Selector types.\n");
|
|
p1(";\n");
|
|
p1("\n");
|
|
p2("SEL_TYPE_NP",SEL_TYPE_NP);
|
|
|
|
//
|
|
// Usermode callout frame
|
|
//
|
|
DisableInc (HAL386);
|
|
genCom("Usermode callout frame definitions");
|
|
p2("CuInStk", OFFSET(KCALLOUT_FRAME, InStk));
|
|
p2("CuTrFr", OFFSET(KCALLOUT_FRAME, TrFr));
|
|
p2("CuCbStk", OFFSET(KCALLOUT_FRAME, CbStk));
|
|
p2("CuEdi", OFFSET(KCALLOUT_FRAME, Edi));
|
|
p2("CuEsi", OFFSET(KCALLOUT_FRAME, Esi));
|
|
p2("CuEbx", OFFSET(KCALLOUT_FRAME, Ebx));
|
|
p2("CuEbp", OFFSET(KCALLOUT_FRAME, Ebp));
|
|
p2("CuRet", OFFSET(KCALLOUT_FRAME, Ret));
|
|
p2("CuOutBf", OFFSET(KCALLOUT_FRAME, OutBf));
|
|
p2("CuOutLn", OFFSET(KCALLOUT_FRAME, OutLn));
|
|
EnableInc (HAL386);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
VOID
|
|
p1 (PUCHAR a)
|
|
{
|
|
if (OutputEnabled & KS386) {
|
|
fprintf(OutKs386,a);
|
|
}
|
|
|
|
if (OutputEnabled & HAL386) {
|
|
if ( OutHal386 ) {
|
|
fprintf(OutHal386,a);
|
|
}
|
|
}
|
|
}
|
|
|
|
VOID
|
|
p2 (PUCHAR a, LONG b)
|
|
{
|
|
if (OutputEnabled & KS386) {
|
|
fprintf(OutKs386, "%s equ 0%lXH\n", a, b);
|
|
}
|
|
|
|
if (OutputEnabled & HAL386) {
|
|
if ( OutHal386 ) {
|
|
fprintf(OutHal386, "%s equ 0%lXH\n", a, b);
|
|
}
|
|
}
|
|
}
|
|
|
|
VOID
|
|
p2a (PUCHAR b, LONG c)
|
|
{
|
|
if (OutputEnabled & KS386) {
|
|
fprintf(OutKs386, b, c);
|
|
}
|
|
|
|
if (OutputEnabled & HAL386) {
|
|
if ( OutHal386 ) {
|
|
fprintf(OutHal386, b, c);
|
|
}
|
|
}
|
|
}
|