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435 lines
11 KiB
435 lines
11 KiB
/*++
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Copyright (c) 1992 BusLogic, Inc.
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Module Name:
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buslogic.h
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Abstract:
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This module contains the structures, specific to the BusLogic
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host bus adapters, used by the SCSI miniport driver. Data structures
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that are part of standard ANSI SCSI will be defined in a header
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file that will be available to all SCSI device drivers.
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Revision History:
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--*/
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#include "scsi.h"
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///////////////////////////////////////////////////////////////////////////////
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//
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// CCB - BusLogic SCSI Command Control Block
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//
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// The CCB is a wrapper for the CDB (Command Descriptor Block)
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// and specifies detailed information about a SCSI command.
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Byte 0 Command Control Block Operation Code
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//
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// Byte 1 Address and Direction Control
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//
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// Byte 2 SCSI_Command_Length - Length of SCSI CDB
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//
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// Byte 3 Request Sense Allocation Length
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//
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// Bytes 4, 5,6 & 7 Data Length // Data transfer byte count
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//
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// Bytes 8,9, A, & B Data Pointer // SG List or Data Bfr Ptr
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//
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// Bytes C & D Reserved
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//
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// Byte E Host Status // Host Adapter status
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//
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// Byte F Target Status // Target status
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//
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// Byte 10 Target ID // Target ID
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//
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// Byte 11 LUN
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//
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// Byte 12 thru 1D SCSI CDB // Command Desc. Block
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//
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// Byte 1E Reserved
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//
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// Byte 1F Link ID
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//
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// Byte 20 thru 23 Link pointer // physical link ptr
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//
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// Byte 24 thru 27 Sense pointer // phys. ptr to req. sense
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//
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// Driver-specific fields follow //
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//
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// Operation Code Definitions
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//
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#define SCSI_INITIATOR_COMMAND 0x00
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#define TARGET_MODE_COMMAND 0x01
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#define SCATTER_GATHER_COMMAND 0x02
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#define RESET_COMMAND 0x81
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//
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// Control Byte (byte 1) definitions
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//
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#define CCB_DATA_XFER_OUT 0x10 // Write
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#define CCB_DATA_XFER_IN 0x08 // Read
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#define CCB_LUN_MASK 0x07 // Logical Unit Number
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//
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// Request Sense Definitions
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//
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#define FOURTEEN_BYTES 0x00 // Request Sense Buffer size
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#define NO_AUTO_REQUEST_SENSE 0x01 // No Request Sense Buffer
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///////////////////////////////////////////////////////////////////////////////
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//
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// Scatter/Gather Segment List Definitions
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Adapter limits
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//
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#define MAX_SG_DESCRIPTORS 32
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#define MAX_TRANSFER_SIZE 256 * 1024
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//
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// Scatter/Gather Segment Descriptor Definition
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//
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typedef struct _SGD {
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ULONG Length;
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ULONG Address;
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} SGD, *PSGD;
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typedef struct _BL_CONTEXT {
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ULONG AdapterCount;
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ULONG PCIDevId;
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} BL_CONTEXT, *PBL_CONTEXT;
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typedef struct _SDL {
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SGD Sgd[MAX_SG_DESCRIPTORS];
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} SDL, *PSDL;
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#define SEGMENT_LIST_SIZE MAX_SG_DESCRIPTORS * sizeof(SGD)
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///////////////////////////////////////////////////////////////////////////////
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//
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// CCB Typedef
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//
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typedef struct _CCB *PCCB;
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typedef struct _CCB {
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UCHAR OperationCode;
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UCHAR ControlByte;
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UCHAR CdbLength;
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UCHAR RequestSenseLength;
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ULONG DataLength;
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PVOID DataPointer;
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USHORT CcbRes0;
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UCHAR HostStatus;
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UCHAR TargetStatus;
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UCHAR TargID;
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UCHAR Lun;
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UCHAR Cdb[12];
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UCHAR CcbRes1;
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UCHAR LinkIdentifier;
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PVOID LinkPointer;
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ULONG SensePointer;
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SDL Sdl;
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PVOID SrbAddress;
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PVOID AbortSrb;
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PCCB NxtActiveCCB;
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} CCB;
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//
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// CCB and request sense buffer
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//
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#define CCB_SIZE sizeof(CCB)
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//
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// Host Adapter Command Operation Codes
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//
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#define AC_NO_OPERATION 0x00
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#define AC_MAILBOX_INITIALIZATION 0x01
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#define AC_START_SCSI_COMMAND 0x02
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#define AC_START_BIOS_COMMAND 0x03
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#define AC_ADAPTER_INQUIRY 0x04
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#define AC_ENABLE_MBO_AVAIL_INT 0x05
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#define AC_SET_SELECTION_TIMEOUT 0x06
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#define AC_SET_BUS_ON_TIME 0x07
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#define AC_SET_BUS_OFF_TIME 0x08
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#define AC_SET_TRANSFER_SPEED 0x09
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#define AC_RET_INSTALLED_DEVICES 0x0A
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#define AC_RET_CONFIGURATION_DATA 0x0B
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#define AC_ENABLE_TARGET_MODE 0x0C
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#define AC_RETURN_SETUP_DATA 0x0D
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#define AC_WRITE_CHANNEL_2_BUFFER 0x1A
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#define AC_READ_CHANNEL_2_BUFFER 0x1B
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#define AC_WRITE_FIFO_BUFFER 0x1C
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#define AC_READ_FIFO_BUFFER 0x1D
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#define AC_ECHO_COMMAND_DATA 0x1F
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#define AC_SET_ADAPTER_OPTIONS 0x21
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#define AC_EXTENDED_SETUP_INFO 0x8D
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#define AC_EXTENDED_FWREV 0x84
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#define AC_MBOX_EXTENDED_INIT 0x81
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#define AC_ISA_COMPATIBLE_SUPPORT 0x95
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#define AC_WIDE_SUPPORT 0x96
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#define AC_PCI_INFO 0x86
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#define AC_INT_GENERATION_STATE 0x25
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#define DISABLE_ISA_MAPPING 0x6 // cmd 0x95 above
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#define ENABLE_INTS 0x1 // cmd 0x25 above
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#define DISABLE_INTS 0x0 // cmd 0x25 above
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//
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// Host status byte
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//
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#define CCB_COMPLETE 0x00 // CCB completed without error
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#define CCB_LINKED_COMPLETE 0x0A // Linked command completed
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#define CCB_LINKED_COMPLETE_INT 0x0B // Linked complete with interrupt
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#define CCB_SELECTION_TIMEOUT 0x11 // Set SCSI selection timed out
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#define CCB_DATA_OVER_UNDER_RUN 0x12
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#define CCB_UNEXPECTED_BUS_FREE 0x13 // Target dropped SCSI BSY
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#define CCB_PHASE_SEQUENCE_FAIL 0x14 // Target bus phase sequence failure
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#define CCB_BAD_MBO_COMMAND 0x15 // MBO command not 0, 1 or 2
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#define CCB_INVALID_OP_CODE 0x16 // CCB invalid operation code
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#define CCB_BAD_LINKED_LUN 0x17 // Linked CCB LUN different from first
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#define CCB_INVALID_DIRECTION 0x18 // Invalid target direction
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#define CCB_DUPLICATE_CCB 0x19 // Duplicate CCB
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#define CCB_INVALID_CCB 0x1A // Invalid CCB - bad parameter
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//
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// DMA Transfer Speeds
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//
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#define DMA_SPEED_50_MBS 0x00
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//
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// LUN byte definitions
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//
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#define ENABLE_TQ 0x20 /* bit 5 in bytes 17 of CCB (LUN) */
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#define QUEUEHEAD 0x40 /* Head of Queue tag */
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#define ORDERED 0x80 /* Ordered Queue tag */
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#define SIMPLE 0x00 /* Simple Queue tag */
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//
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// I/O Port Interface
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//
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typedef struct _BASE_REGISTER {
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UCHAR StatusRegister;
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UCHAR CommandRegister;
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UCHAR InterruptRegister;
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} BASE_REGISTER, *PBASE_REGISTER;
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//
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// Base+0 Write: Control Register
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//
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#define IOP_HARD_RESET 0x80 // bit 7
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#define IOP_SOFT_RESET 0x40 // bit 6
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#define IOP_INTERRUPT_RESET 0x20 // bit 5
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#define IOP_SCSI_BUS_RESET 0x10 // bit 4
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//
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// Base+0 Read: Status
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//
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#define IOP_SELF_TEST 0x80 // bit 7
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#define IOP_INTERNAL_DIAG_FAILURE 0x40 // bit 6
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#define IOP_MAILBOX_INIT_REQUIRED 0x20 // bit 5
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#define IOP_SCSI_HBA_IDLE 0x10 // bit 4
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#define IOP_COMMAND_DATA_OUT_FULL 0x08 // bit 3
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#define IOP_DATA_IN_PORT_FULL 0x04 // bit 2
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#define IOP_INVALID_COMMAND 0X01 // bit 1
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//
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// Base+1 Write: Command/Data Out
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//
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//
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// Base+1 Read: Data In
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//
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//
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// Base+2 Read: Interrupt Flags
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//
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#define IOP_ANY_INTERRUPT 0x80 // bit 7
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#define IOP_SCSI_RESET_DETECTED 0x08 // bit 3
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#define IOP_COMMAND_COMPLETE 0x04 // bit 2
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#define IOP_MBO_EMPTY 0x02 // bit 1
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#define IOP_MBI_FULL 0x01 // bit 0
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///////////////////////////////////////////////////////////////////////////////
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//
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// Mailbox Definitions
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Mailbox Definition
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//
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#define MB_COUNT 32 // number of mailboxes
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//
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// Mailbox Out
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//
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typedef struct _MBO {
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ULONG Address;
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UCHAR MboRes[3];
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UCHAR Command;
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} MBO, *PMBO;
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//
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// MBO Command Values
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//
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#define MBO_FREE 0x00
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#define MBO_START 0x01
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#define MBO_ABORT 0x02
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//
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// Mailbox In
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//
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typedef struct _MBI {
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ULONG Address;
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UCHAR MbiHStat;
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UCHAR MbiTStat;
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UCHAR MbiRes;
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UCHAR Status;
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} MBI, *PMBI;
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//
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// MBI Status Values
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//
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#define MBI_FREE 0x00
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#define MBI_SUCCESS 0x01
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#define MBI_ABORT 0x02
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#define MBI_NOT_FOUND 0x03
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#define MBI_ERROR 0x04
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//
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// Mailbox Initialization
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//
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typedef struct _MAILBOX_INIT {
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ULONG Address;
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UCHAR Count;
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} MAILBOX_INIT, *PMAILBOX_INIT;
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//
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// The following structure is allocated
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// from noncached memory as data will be DMA'd to
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// and from it.
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//
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typedef struct _NONCACHED_EXTENSION {
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//
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// Physical base address of mailboxes
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//
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ULONG MailboxPA;
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//
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// Mailboxes
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//
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MBO Mbo[MB_COUNT];
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MBI Mbi[MB_COUNT];
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} NONCACHED_EXTENSION, *PNONCACHED_EXTENSION;
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//
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// Device extension
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//
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typedef struct _CARD_STRUC {
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PNONCACHED_EXTENSION MailBoxArray; /* NonCached Extension */
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PBASE_REGISTER BaseIoAddress; /* Base I/O Address */
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PMBO CurrMBO; /* Current Mbox Out */
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PMBO StartMBO; /* First Mbox Out */
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PMBO LastMBO; /* Last Mbox Out */
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PMBI CurrMBI; /* Current Mbox In */
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PMBI StartMBI; /* First Mbox In */
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PMBI LastMBI; /* Last Mbox In */
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ULONG Flags;
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UCHAR BusType; /* ISA/EISA/ or MCA */
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UCHAR BusNum; /* SCSI bus number */
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UCHAR HostTargetId; /* HBA Target ID */
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UCHAR Reserved; /* explicit DWORD align */
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} CARD_STRUC, *PCARD_STRUC;
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//
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// CardStruc BusType definitions
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//
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#define ISA_HBA 'A'
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#define EISA_HBA 'E'
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#define MCA_HBA 'M'
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//
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// CardStruc Flags definitions
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//
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#define TAGGED_QUEUING 0x1000
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#define REINIT_REQUIRED 0x100
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#define WIDE_ENABLED 0x10
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#define OS_SUPPORTS_WIDE 0x200
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//
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// Logical unit extension
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//
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typedef struct _DEV_STRUC {
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PCCB CurrentCCB; /* pointer to most recent active CCB */
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UCHAR NumActive;
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} DEV_STRUC, *PDEV_STRUC;
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#define MAXACTIVE 2
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#define MAXACTIVE_TAGGED 8
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//
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// miscellaneous definitions
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//
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#define SIMPLE_TAG 0x20
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#define HEAD_OF_QUEUE 0x21
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#define ORDERED_TAG 0x22
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#define LEVEL_TRIG 0x40
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#define RETURN_FOUND_VESA 4
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#define PORTMASK 0x7
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#define MAXIMUM_EISA_SLOTS 0x10
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#define EISA_ADDRESS_BASE 0x0C80
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typedef struct _EISA_ID {
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UCHAR BoardId[4];
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UCHAR Reserved[8];
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UCHAR IOPort[1];
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} *PEISA_ID;
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