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202 lines
5.6 KiB
202 lines
5.6 KiB
//-----------------------------------------------------------------------
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//
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// SL386.H
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//
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// Trantor SL386 Definitions File
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//
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// Revisions:
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// 04-07-93 KJB First, taken from SL386.def.
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// 05-17-93 KJB Added missing prototype.
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//
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// 80386SL unit configuration spaces
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//
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// Perform the following sequence of IOs to unlock the
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// CPUPWRMODE register.
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//
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// byte write 0h to port 23h
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// byte write 80h to port 22h
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// word write 0080h to port 22h
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//
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// CPUPWRMODE bit definitions:
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//
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// Bit 15: IOCFGOPN
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//
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// Bits 14-9: Not defined here
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//
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// Bit 8: CPUCNFG lock
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//
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// Bits 7-4: Not defined here
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//
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// Bits 3,2: UID1 UID0
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// 0 0 CMCU (Mem ctlr unit cfg space)
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// 0 1 CU (Cache unit cfg space)
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// 1 0 IBU (Internal bus unit cfg space)
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// 1 1 EBU (External bus unit cfg space)
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//
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// Bit 1: Unit enable
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//
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// Bit 0: Unlock status
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//-----------------------------------------------------------------------
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#define SL_CPUPWRMODE 0x22
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//cpupwrmode_rec record pm_iocfgopn:1,pm_resv:6,pm_cfg_lock:1,
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//pm_resv1:4,pm_uid:2,pm_ue:1,pm_ls:1
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#define PM_IOCFGOPN 0x8000
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#define PM_RESV 0x7e00
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#define PM_CFG_LOCK 0x0100
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#define PM_RESV1 0x00f0
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#define PM_UID 0x00c0
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#define PM_UE 0x0002
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#define PM_LS 0x0001
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#define PM_UID_CMCU 0x00
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#define PM_UID_CU 0x40
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#define PM_UID_IBU 0x80
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#define PM_UID_EBU 0xc0
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//-----------------------------------------------------------------------
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// 80386SL configuration space
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//-----------------------------------------------------------------------
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// Read the following I/O addresses in the specified order to
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// enable the 386SL configuration space.
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#define SL_CNFG_ENA1 0x0fc23
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#define SL_CNFG_ENA2 0x0f023
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#define SL_CNFG_ENA3 0x0c023
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#define SL_CNFG_ENA4 0x00023
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#define SL_CFG_STATUS 0x23 //Config space status
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#define SL_CFG_INDEX 0x24 //Config space index
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#define SL_CFG_DATA 0x25 //Config space data
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#define SL_IDXLCK 0x0fa //Cfg index lock register
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#define SL_IDXLCK_VAL 0x01 //default value for same
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//-----------------------------------------------------------------------
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// CFGR2 bit definitions
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//
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// Bit 7: COMA_MIDI
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//
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// Bits 6-4: AIRQ2 AIRQ1 AIRQ0
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// 0 0 0 COMA IRQ3
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// 0 0 1 COMA IRQ4
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// 0 1 0 COMA IRQ10
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// 0 1 1 COMA IRQ11
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// 1 0 0 COMA IRQ12
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// 1 0 1 COMA IRQ15
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//
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// Bit 3: SFIO_EN
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//
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// Bit 2: FD_SEL
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//
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// Bit 1: HD_SEL
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//
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// Bit 0: PS2_EN
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//-----------------------------------------------------------------------
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#define SL_CFGR2 0x61 //CFGR2 register index
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//cfgr2_rec record c2_midi:1,c2_airq:3,c2_sfio:1,c2_fd:1,c2_hd:1,c2_ps2:1
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#define C2_MIDI 0x80
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#define C2_AIRQ 0x70
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#define C2_SFIO 0x08
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#define C2_FD 0x04
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#define C2_HD 0x02
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#define C2_PS2 0x01
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//-----------------------------------------------------------------------
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// Special feature control registers
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//-----------------------------------------------------------------------
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#define SL_SF_INDEX 0x0ae //Special feature index
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#define SL_SF_DATA 0x0af //Special feature data
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#define SL_SFS_DISABLE 0x0f9 //Special feature disable
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#define SL_SFS_ENABLE 0x0fb //Special feature enable
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//-----------------------------------------------------------------------
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// Bit definitions for FPP control register.
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//
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// Bit 7: 0 = ISA or PS/2 modes
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// 1 = FAST_MODE (EPP)
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//
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// Bit 6: 0 = unidirectional mode
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// 1 = bidirectional mode
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//
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// Bits 5,4: CTL5 CTL4
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// 0 0 Parallel port disabled
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// 0 1 Parallel port LPT1 (378h), IRQ7
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// 1 0 Parallel port LPT2 (278h), IRQ5
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// 1 1 Reserved
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//
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// Bits 0-3: Reserved (0)
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//-----------------------------------------------------------------------
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#define SL_FPP_CNTL 0x02 //SFS index for FPP_CNTL
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// fpp_cntl_rec record fpp_fm:1,fpp_em:1,fpp_ctl:2,fpp_resv:4
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#define FPP_FM 0x80
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#define FPP_EM 0x40
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#define FPP_CTL 0x03
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#define FPP_CTL_DIS 0
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#define FPP_CTL_LPT1 0x10
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#define FPP_CTL_LPT2 0x20
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#define FPP_CTL_RESV 0x30
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//-----------------------------------------------------------------------
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// Bit definitions for PPCONFIG register.
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//
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// Bit 7: 0 = unidirectional mode
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// 1 = bidirectional mode
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//
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// Bit 6,5: LPTSL1 LPTSL0
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// 0 0 Selects LPT1 (IO base 378h)
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// 0 1 Selects LPT2 (IO base 278h)
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// 1 0 Selects LPT3 (IO base 3bch)
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// 1 1 Disables internal parallel port
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//
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// Bits 0-4: Reserved
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//-----------------------------------------------------------------------
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#define SL_PPCONFIG 0x102 //PPCONFIG reg
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//ppconfig_rec record ppc_bid:1,ppc_sel:2,ppc_resv:5
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#define PPC_BID 0x80
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#define PPC_SEL 0x60
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#define PPC_SEL_POS 0x05
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#define PPC_SEL_LPT1 0x00
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#define PPC_SEL_LPT2 0x20
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#define PPC_SEL_LPT3 0x40
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#define PPC_SEL_DIS 0x60
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//-----------------------------------------------------------------------
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// EPP Parallel port register offsets
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//-----------------------------------------------------------------------
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#define EPP_DATA 0x0 //read/write
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#define EPP_STATUS 0x1 //read-only
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#define EPP_CTL 0x2 //read/write
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#define EPP_AUTO_ADDRESS 0x3 //read/write
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#define EPP_AUTO_DATA 0x4 //read/write (also at 5h-7h)
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//
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// Exported functions.
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//
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BOOLEAN SL386EnableEPP(VOID );
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