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1418 lines
34 KiB
1418 lines
34 KiB
//-----------------------------------------------------------------------
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//
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// EP3C.C
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//
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// Trantor EP3C access file.
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//
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// Revisions:
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// 03-31-93 KJB First.
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// 04-09-93 KJB Changed "in edx,al" and "out edx,al" references to
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// use only the dx register: in al,dx.
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// Changed loop instructions to dec ecx, jnz.
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// 04-21-93 KJB Fixed initialization error for os/2: static
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// variables must be initialized.
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// 05-05-93 KJB Disable Checking for EPP port for debug purposes.
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// TEMPORARY.
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// 05-05-93 KJB Added ReadFifoUni/BiDirSlow routines to do P_BUSY
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// checking to allow bytes to get ready.
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// 05-11-93 KJB Added WriteFifoUniDirSlow routine to do P_BUSY
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// checking to allow bytes to get ready.
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// 05-17-93 JAP Made in-line assemble routines conditionally coded.
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// Only #ifdef WINNT will these routines be read in.
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// Otherwise, look in ep3c2.asm.
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// 05-17-93 KJB Fixed some compiler warnings.
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//
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//-----------------------------------------------------------------------
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#include CARDTXXX_H
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// Local Functions
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VOID EP3CSetPrinterMode(PADAPTER_INFO g, UCHAR data, UCHAR control);
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VOID EP3CSetScsiMode(PADAPTER_INFO g, PUCHAR data, PUCHAR control);
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USHORT EP3CReadBytesFastBiDir(PADAPTER_INFO g, PUCHAR pbytes,
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ULONG len, PULONG pActualLen, UCHAR phase);
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USHORT EP3CReadBytesFastUniDir(PADAPTER_INFO g, PUCHAR pbytes,
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ULONG len, PULONG pActualLen, UCHAR phase);
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VOID EP3CSetRegisterUniDir(PADAPTER_INFO g, UCHAR reg);
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VOID EP3CSetRegisterEPP(PADAPTER_INFO g, UCHAR reg);
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BOOLEAN EP3CCheckAdapterType(PADAPTER_INFO g);
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VOID EP3CSetParallelPortType(PADAPTER_INFO g);
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VOID EP3CReadFifoUniDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes);
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VOID EP3CReadFifoBiDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes);
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VOID EP3CReadFifoEPP(PBASE_REGISTER baseIoAddress, PUCHAR pbytes);
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VOID EP3CWriteFifoUniDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes);
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VOID EP3CWriteFifoEPP(PBASE_REGISTER baseIoAddress, PUCHAR pbytes);
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// for writes, uni-directional is the same as bi-directional
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#define EP3CSetRegisterBiDir EP3CSetRegisterUniDir
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#define EP3CWriteFifoBiDir EP3CWriteFifoUniDir
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#define EP3CWriteDataRegisterBiDir EP3CWriteDataRegisterUniDir
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#define EP3CWriteControlRegisterBiDir EP3CWriteControlRegisterUniDir
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/// for control registers, epp is the same as bi-dir
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#define EP3CWriteControlRegisterEPP EP3CWriteControlRegisterBiDir
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#define EP3CReadControlRegisterEPP EP3CReadControlRegisterBiDir
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// local redefinitions
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#define EP3CPortPut(g, reg, value) \
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(*(g->EP3CWriteControlRegister))(g,reg,value)
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#define EP3CPortGet(g, reg, value) \
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(*(g->EP3CReadControlRegister))(g, value)
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//
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// VOID EP3CPortSet
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//
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// Or's bits into an EP3C register.
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//
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VOID EP3CPortSet(PADAPTER_INFO g, UCHAR reg, UCHAR value)
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{
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UCHAR tmp;
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EP3CPortGet(g,reg,&tmp);
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tmp |= value;
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EP3CPortPut(g,reg,tmp);
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}
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//
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// VOID EP3CPortClear
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//
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// Clears all bits in the EP3C register with value.
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//
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VOID EP3CPortClear(PADAPTER_INFO g, UCHAR reg, UCHAR value)
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{
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UCHAR tmp;
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EP3CPortGet(g,reg,&tmp);
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tmp &= (value ^ 0xff);
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EP3CPortPut(g,reg,tmp);
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}
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//
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// VOID EP3CPortTest
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//
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// Tests bits in value with the EP3C register.
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//
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BOOLEAN EP3CPortTest(PADAPTER_INFO g, UCHAR reg, UCHAR value)
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{
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UCHAR tmp;
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EP3CPortGet(g,reg,&tmp);
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return (tmp & value);
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}
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//
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// VOID EP3CSetRegisterUniDir(PADAPTER_INFO g, UCHAR reg)
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//
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// Sets the register that will be accessed.
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//
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VOID EP3CSetRegisterUniDir(PADAPTER_INFO g, UCHAR reg)
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{
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UCHAR tmp;
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// write to adr reg 1
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tmp = (reg & EP3C_ADRS);
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EP3CPortPut(g,EP3C_AREG1,tmp);
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}
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//
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// VOID EP3CSetRegisterEPP(PADAPTER_INFO g, UCHAR reg)
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//
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// Sets the register that will be accessed.
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//
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VOID EP3CSetRegisterEPP(PADAPTER_INFO g, UCHAR reg)
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{
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ParallelPortPut(g->BaseIoAddress,EPP_AUTO_ADDRESS,reg);
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}
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//
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// VOID EP3CWriteControlRegisterUniDir
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//
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// Writes to an adr register of the ep3c using a uni-directional port.
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//
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VOID EP3CWriteControlRegisterUniDir(PADAPTER_INFO g, UCHAR areg,
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UCHAR value)
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{
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UCHAR tmp;
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// output the value and register to the parallel data reg
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tmp = value | areg;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,tmp);
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// write to ep3c
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp & (0xff ^ P_BUFEN);
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tmp = tmp | P_STB;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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tmp = tmp | P_SLC;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// negate P_STB & P_SLC, to end write
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tmp = tmp & (0xff ^ (P_STB | P_SLC));
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// note: we leave P_BUFEN asserted.
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}
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//
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// VOID EP3CReadControlRegisterBiDir
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//
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// Reads from an adr register of the ep3c using a bi-directional port.
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// NOTE: always read areg1 since areg2 is write-only.
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//
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VOID EP3CReadControlRegisterBiDir(PADAPTER_INFO g, PUCHAR value)
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{
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UCHAR tmp;
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// negate P_BUFEN and assert P_SLC
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp | P_BUFEN | P_SLC;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// read data register
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ParallelPortGet(g->BaseIoAddress,PARALLEL_DATA,value);
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// negate P_BUFEN and negate P_SLC
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tmp = (tmp & ((P_SLC | P_BUFEN) ^ 0xff));
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// tmp = (tmp & (P_SLC ^ 0xff)) | P_BUFEN;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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}
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//
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// VOID EP3CReadControlRegisterUniDir
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//
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// Reads from an adr register of the ep3c using a uni-directional port.
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// NOTE: always read areg1 since areg2 is write-only.
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//
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VOID EP3CReadControlRegisterUniDir(PADAPTER_INFO g, PUCHAR value)
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{
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UCHAR tmp;
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UCHAR tmp1;
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// select high nibble
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ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,0x80);
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// assert P_BUFEN and assert P_SLC
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp & (P_BUFEN ^ 0xff) | P_SLC;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// read high nibble
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ParallelPortGet(g->BaseIoAddress,PARALLEL_STATUS,&tmp);
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// compute high nibble
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tmp = (tmp << 1) & 0xf0;
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// select low nibble
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ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,0x00);
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// read low nibble
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ParallelPortGet(g->BaseIoAddress,PARALLEL_STATUS,&tmp1);
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// compute low nibble
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tmp1 = (tmp1 >> 3) & 0x0f;
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// compute and return byte
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*value = tmp1 | tmp;
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// leave P_BUFEN asserted, negate P_SLC
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp & ((P_BUFEN | P_SLC) ^ 0xff);
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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}
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//
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// VOID EP3CReadDataRegisterUniDir
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//
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// Reads a byte from a register thru the ep3c, using uni-dir mode.
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//
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VOID EP3CReadDataRegisterUniDir(PADAPTER_INFO g,
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UCHAR reg, PUCHAR byte)
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{
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UCHAR tmp;
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UCHAR tmp1;
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// set the register we want to access
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(*(g->EP3CSetRegister))(g, reg);
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// select high nibble
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ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,0x80);
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// assert P_BUFEN and assert P_AFX
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp & (P_BUFEN ^ 0xff) | P_AFX;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// read high nibble
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ParallelPortGet(g->BaseIoAddress,PARALLEL_STATUS,&tmp);
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// compute high nibble
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tmp = (tmp << 1) & 0xf0;
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// select low nibble
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ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,0x00);
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// read low nibble
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ParallelPortGet(g->BaseIoAddress,PARALLEL_STATUS,&tmp1);
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// compute low nibble
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tmp1 = (tmp1 >> 3) & 0x0f;
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// compute and return byte
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*byte = tmp1 | tmp;
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// leave P_BUFEN asserted, negate P_AFX
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp & ((P_BUFEN | P_AFX) ^ 0xff);
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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}
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//
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// VOID EP3CReadDataRegisterBiDir
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//
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// Reads a byte from a register thru the EP3C, using bi-dir mode.
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//
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VOID EP3CReadDataRegisterBiDir(PADAPTER_INFO g,
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UCHAR reg, PUCHAR byte)
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{
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UCHAR tmp;
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// set the register we want to access
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(*(g->EP3CSetRegister))(g, reg);
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// negate P_BUFEN, assert P_AFX
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp | P_BUFEN | P_AFX;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// read the data byte
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ParallelPortGet(g->BaseIoAddress,PARALLEL_DATA,byte);
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// negate P_BUFEN, and P_AFX
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tmp = tmp & ((P_BUFEN | P_AFX) ^ 0xff);
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// tmp = tmp | P_BUFEN & (P_AFX ^ 0xff);
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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}
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//
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// VOID EP3CReadDataRegisterEPP
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//
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// Reads a byte from a register thru the EP3C, using epp mode.
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//
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VOID EP3CReadDataRegisterEPP(PADAPTER_INFO g,
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UCHAR reg, PUCHAR byte)
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{
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// set the register we want to access
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(*(g->EP3CSetRegister))(g, reg);
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// read the data byte
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ParallelPortGet(g->BaseIoAddress,EPP_AUTO_DATA,byte);
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}
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//
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// VOID EP3CWriteDataRegisterUniDir
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//
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// Writes the a register thru the EP3C.
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//
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VOID EP3CWriteDataRegisterUniDir(PADAPTER_INFO g,
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UCHAR reg, UCHAR byte)
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{
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UCHAR tmp;
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// set the register we want to access
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(*(g->EP3CSetRegister))(g, reg);
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// output the byte on the data lines
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ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,byte);
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// assert P_BUFEN and P_STB
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ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,&tmp);
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tmp = tmp & (0xff ^ P_BUFEN) | P_STB;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// assert P_AFX
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tmp = tmp | P_AFX;
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// negate P_STB & P_AFX, to end write
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tmp = tmp & (0xff ^ (P_STB | P_AFX));
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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// negate P_BUFEN
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// tmp = tmp | P_BUFEN;
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// ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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}
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//
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// VOID EP3CWriteDataRegisterEPP
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//
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// Writes the a register thru the EP3C.
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//
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VOID EP3CWriteDataRegisterEPP(PADAPTER_INFO g,
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UCHAR reg, UCHAR byte)
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{
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// set the register we want to access
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(*(g->EP3CSetRegister))(g, reg);
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// output the byte on the data lines
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ParallelPortPut(g->BaseIoAddress,EPP_AUTO_DATA,byte);
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}
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//
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// VOID EP3CReadFifoEPP
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//
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// Reads bytes for epp parallel port from the 53c400
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// 128 byte buffer. The register must already be set the the
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// 53c400 buffer register.
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//
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VOID EP3CReadFifoEPP(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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{
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ScsiPortReadPortBufferUshort (
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(PUSHORT)&(((PUCHAR)baseIoAddress)[EPP_AUTO_DATA]),
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(PUSHORT)pbytes, 64);
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}
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//
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// VOID EP3CWriteFifoEPP
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//
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// Writes bytes thru epp parallel port to the 53c400
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// 128 byte buffer. The register must already be set the the
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// 53c400 buffer register.
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//
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VOID EP3CWriteFifoEPP(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
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{
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ScsiPortWritePortBufferUshort (
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(PUSHORT)&(((PUCHAR)baseIoAddress)[EPP_AUTO_DATA]),
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(PUSHORT)pbytes, 64);
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}
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//
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// VOID EP3CDisableInterrupt
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//
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// Disables the interrupt.
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//
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VOID EP3CDisableInterrupt(PADAPTER_INFO g)
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{
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// set global flag for EP3CSetPrinterMode
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g->EnableInterrupt = FALSE;
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// see if the EP3C_IRQEN is asserted, if so clear it
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if (EP3CPortTest(g,EP3C_AREG1,EP3C_IRQEN)) {
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// clear the interrupts
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// NOTE: a positive going edge toggles the state of EP3C_IRQEN
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EP3CPortSet(g, EP3C_AREG1, EP3C_IRQEN);
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EP3CPortClear(g, EP3C_AREG1, EP3C_IRQEN);
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}
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// finally, we can disable the core interrupts
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N53C400DisableInterrupt(g);
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}
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//
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// VOID EP3CEnableInterrupt
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//
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// Enables the interrupt.
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//
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VOID EP3CEnableInterrupt(PADAPTER_INFO g)
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{
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UCHAR tmp;
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// set global flag for EP3CSetPrinterMode
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g->EnableInterrupt = TRUE;
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// see if the EP3C_IRQEN is not asserted, if so assert it
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EP3CPortGet(g, EP3C_AREG1, &tmp);
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if (!(tmp & EP3C_IRQEN)) {
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// set the interrupts
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// NOTE: a positive going edge toggles the state of EP3C_IRQEN
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EP3CPortPut(g, EP3C_AREG1, EP3C_IRQEN);
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EP3CPortPut(g, EP3C_AREG1, 0);
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}
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// finally, we can disable the core interrupts
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N53C400EnableInterrupt(g);
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}
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//
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// EP3CSetPrinterMode
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//
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// This routine sets the EP3C to printer pass through mode. This is the
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// default mode and should be set after the brief use of scsi mode.
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//
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VOID EP3CSetPrinterMode(PADAPTER_INFO g, UCHAR data, UCHAR control)
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{
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UCHAR tmp;
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// restore data register
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ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,data);
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// restore control register
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// leave p_init negated, P_BUFEN asserted
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// also set P_IRQEN based on g->EnableInterrupt
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tmp = control | P_INIT & (P_BUFEN ^ 0xff);
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if (g->EnableInterrupt) {
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tmp = tmp | P_IRQEN;
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} else {
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tmp = tmp & (P_IRQEN ^ 0xff);
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}
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ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
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}
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//
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// EP3CSetScsiMode
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//
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// This routine sets the EP3C into scsi mode. Now the parallel port can
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// be used to send commands the the n5380. This mode should be set only
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// briefly during when the scsi command is being executed.
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//
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VOID EP3CSetScsiMode(PADAPTER_INFO g, PUCHAR data, PUCHAR control)
|
|
{
|
|
UCHAR tmp;
|
|
USHORT i;
|
|
|
|
// save parallel data
|
|
ParallelPortGet(g->BaseIoAddress,PARALLEL_DATA,data);
|
|
|
|
// zero data register
|
|
ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,0);
|
|
|
|
// save parallel control
|
|
ParallelPortGet(g->BaseIoAddress,PARALLEL_CONTROL,control);
|
|
*control = *control & (P_BUFEN ^ 0xff);
|
|
|
|
// store current interrupt state
|
|
|
|
g->EnableInterrupt = (*control & P_IRQEN);
|
|
|
|
// put our data pattern on the data bus
|
|
ParallelPortPut(g->BaseIoAddress,PARALLEL_DATA,0xf7);
|
|
|
|
// negate P_SLC, P_BUFEN already asserted
|
|
tmp = *control;
|
|
tmp = tmp & (P_SLC ^ 0xff);
|
|
ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
|
|
|
|
// assert init
|
|
tmp = tmp & (P_INIT ^ 0xff);
|
|
ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
|
|
|
|
// assert P_SLC
|
|
tmp = tmp | P_SLC;
|
|
ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
|
|
|
|
// negate P_SLC
|
|
tmp = tmp & (P_SLC ^ 0xff);
|
|
ParallelPortPut(g->BaseIoAddress,PARALLEL_CONTROL,tmp);
|
|
|
|
// set to the appropriate mode: UNI, BI, etc..
|
|
|
|
if (g->ParallelPortType == PT_UNI) {
|
|
EP3CPortPut(g,(UCHAR)EP3C_AREG2,
|
|
(UCHAR)(EP3C_UNIDIR | g->Delay) );
|
|
} else {
|
|
EP3CPortPut(g,EP3C_AREG2,(UCHAR)(0 | g->Delay));
|
|
}
|
|
|
|
// read in the signature bytes
|
|
|
|
for (i=0;i<2;i++) {
|
|
EP3CPortGet(g, EP3C_AREG1, &g->SignatureBytes[i]);
|
|
}
|
|
|
|
}
|
|
|
|
//
|
|
// EP3CCheckAdapter
|
|
//
|
|
// This routine is used to sense the presense of the EP3C adapter out
|
|
// on the Parallel port. It will only detect the adapter if a device
|
|
// is providing termination power.
|
|
//
|
|
BOOLEAN EP3CCheckAdapter(PADAPTER_INFO g)
|
|
{
|
|
BOOLEAN rval = FALSE;
|
|
static CONST UCHAR ParallelPortType = PT_UNI;
|
|
static CONST UCHAR types[] = { PT_EPP, PT_BI, PT_UNI };
|
|
USHORT i;
|
|
|
|
// default the delay to 2 for now
|
|
g->Delay = 7;
|
|
|
|
if (g->ParallelPortType == PT_UNKNOWN) {
|
|
|
|
// try to locate as all types
|
|
|
|
for (i=0;i<3;i++) {
|
|
|
|
g->ParallelPortType = types[i];
|
|
|
|
// do we have a type[i] port?
|
|
|
|
if (rval = EP3CCheckAdapterType(g)) {
|
|
|
|
break;
|
|
|
|
}
|
|
}
|
|
} else {
|
|
|
|
// try only the parallel port type specified
|
|
|
|
rval = EP3CCheckAdapterType(g);
|
|
}
|
|
|
|
return rval;
|
|
}
|
|
|
|
//
|
|
// VOID EP3CSetParallelType
|
|
//
|
|
// Sets this code to use the type of paralle port given by
|
|
// g->ParallePortType, either PT_UNI, PT_BI, or PT_EPP.
|
|
//
|
|
VOID EP3CSetParallelPortType(PADAPTER_INFO g)
|
|
{
|
|
|
|
switch (g->ParallelPortType) {
|
|
case PT_UNI:
|
|
|
|
// set the port type dependent routines
|
|
|
|
g->EP3CWriteControlRegister = EP3CWriteControlRegisterUniDir;
|
|
g->EP3CReadControlRegister = EP3CReadControlRegisterUniDir;
|
|
g->EP3CReadDataRegister = EP3CReadDataRegisterUniDir;
|
|
g->EP3CWriteDataRegister = EP3CWriteDataRegisterUniDir;
|
|
g->EP3CReadFifo = EP3CReadFifoUniDir;
|
|
// g->EP3CReadFifo = EP3CReadFifoUniDirSlow;
|
|
g->EP3CWriteFifo = EP3CWriteFifoUniDir;
|
|
g->EP3CSetRegister = EP3CSetRegisterUniDir;
|
|
|
|
break;
|
|
case PT_BI:
|
|
|
|
// set the port type dependent routines
|
|
|
|
g->EP3CWriteControlRegister = EP3CWriteControlRegisterBiDir;
|
|
g->EP3CReadControlRegister = EP3CReadControlRegisterBiDir;
|
|
g->EP3CReadDataRegister = EP3CReadDataRegisterBiDir;
|
|
g->EP3CWriteDataRegister = EP3CWriteDataRegisterBiDir;
|
|
g->EP3CReadFifo = EP3CReadFifoBiDir;
|
|
// g->EP3CReadFifo = EP3CReadFifoBiDirSlow;
|
|
g->EP3CWriteFifo = EP3CWriteFifoBiDir;
|
|
g->EP3CSetRegister = EP3CSetRegisterBiDir;
|
|
|
|
break;
|
|
|
|
case PT_EPP:
|
|
// set the port type dependent routines
|
|
|
|
g->EP3CWriteControlRegister = EP3CWriteControlRegisterEPP;
|
|
g->EP3CReadControlRegister = EP3CReadControlRegisterEPP;
|
|
g->EP3CReadDataRegister = EP3CReadDataRegisterEPP;
|
|
g->EP3CWriteDataRegister = EP3CWriteDataRegisterEPP;
|
|
g->EP3CReadFifo = EP3CReadFifoEPP;
|
|
g->EP3CWriteFifo = EP3CWriteFifoEPP;
|
|
g->EP3CSetRegister = EP3CSetRegisterEPP;
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
//
|
|
// BOOLEAN EP3CCheckAdapterType
|
|
//
|
|
// Checks for an adapter on a parallel port of the given type.
|
|
//
|
|
BOOLEAN EP3CCheckAdapterType(PADAPTER_INFO g)
|
|
{
|
|
UCHAR data;
|
|
UCHAR control;
|
|
|
|
// if epp type, then try to initialize 386sl code
|
|
if (g->ParallelPortType == PT_EPP) {
|
|
if (!SL386EnableEPP()) {
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
// configure for the correct type of parallel port
|
|
|
|
EP3CSetParallelPortType(g);
|
|
|
|
// set scsi mode, reads signature bytes.
|
|
|
|
EP3CSetScsiMode(g,&data,&control);
|
|
|
|
// set parallel port for use by printer
|
|
|
|
EP3CSetPrinterMode(g,data,control);
|
|
|
|
// compare the signature bytes
|
|
|
|
if ((g->SignatureBytes[0] == 0xe8) && (g->SignatureBytes[1] == 0xff) ) {
|
|
return TRUE;
|
|
}
|
|
|
|
return FALSE;
|
|
}
|
|
|
|
//
|
|
// EP3CDoCommand
|
|
//
|
|
// Called by the main loop to start a scsi command. This functions is the
|
|
// main entry point for all cards. It returns an SRB status code as defined
|
|
// in ..\..\inc\srb.h. A status code of RET_STATUS_PENDING means that the
|
|
// request has been sent to the controller and an interrupt is needed to
|
|
// finish the request. When this interrupt occurs CardFinishCommandInterrupt
|
|
// will be called.
|
|
//
|
|
USHORT EP3CDoCommand(PTSRB t)
|
|
{
|
|
USHORT rval;
|
|
UCHAR data;
|
|
UCHAR control;
|
|
PADAPTER_INFO g = t->pWorkspace;
|
|
|
|
// put the parallel adapter into scsi mode
|
|
|
|
EP3CSetScsiMode(g, &data, &control);
|
|
|
|
// execute the complete command now, without interrupts
|
|
|
|
rval = ScsiDoCommand(t);
|
|
|
|
// put the parallel adapter back to parallel mode
|
|
|
|
EP3CSetPrinterMode(g, data, control);
|
|
return rval;
|
|
}
|
|
|
|
//
|
|
// EP3CStartCommandInterrupt
|
|
//
|
|
// This routines allow the driver to be polled by checking its
|
|
// CardInterrupt by for example using the timer interrupt, since
|
|
// the EP3C does not support interrupts on its own.
|
|
//
|
|
//
|
|
USHORT EP3CStartCommandInterrupt(PTSRB t)
|
|
{
|
|
USHORT rval;
|
|
UCHAR data;
|
|
UCHAR control;
|
|
PADAPTER_INFO g = t->pWorkspace;
|
|
|
|
// put the parallel adapter into scsi mode
|
|
|
|
EP3CSetScsiMode(g, &data, &control);
|
|
|
|
// execute the complete command now, without interrupts
|
|
|
|
rval = ScsiStartCommandInterrupt(t);
|
|
|
|
// put the parallel adapter back to parallel mode
|
|
|
|
EP3CSetPrinterMode(g, data, control);
|
|
|
|
return rval;
|
|
}
|
|
|
|
//
|
|
// EP3CFinishCommandInterrupt
|
|
//
|
|
// This routines allow the driver to be polled by checking its
|
|
// CardInterrupt by for example using the timer interrupt, since
|
|
// the EP3C does not support interrupts on its own.
|
|
//
|
|
//
|
|
USHORT EP3CFinishCommandInterrupt(PTSRB t)
|
|
{
|
|
USHORT rval;
|
|
UCHAR data;
|
|
UCHAR control;
|
|
PADAPTER_INFO g = t->pWorkspace;
|
|
|
|
// put the parallel adapter into scsi mode
|
|
|
|
EP3CSetScsiMode(g, &data, &control);
|
|
|
|
// execute the complete command now, without interrupts
|
|
|
|
rval = ScsiFinishCommandInterrupt(t);
|
|
|
|
// put the parallel adapter back to parallel mode
|
|
|
|
EP3CSetPrinterMode(g, data, control);
|
|
|
|
return rval;
|
|
}
|
|
|
|
//
|
|
// EP3CInterrupt
|
|
//
|
|
// This routines allow the driver to be polled by checking its
|
|
// CardInterrupt by for example using the timer interrupt, since
|
|
// the EP3C does not support interrupts on its own.
|
|
//
|
|
BOOLEAN EP3CInterrupt(PADAPTER_INFO g)
|
|
{
|
|
BOOLEAN rval;
|
|
UCHAR data;
|
|
UCHAR control;
|
|
|
|
// put the parallel adapter into scsi mode
|
|
|
|
EP3CSetScsiMode(g, &data, &control);
|
|
|
|
rval = N5380Interrupt(g);
|
|
|
|
// put the parallel adapter back to parallel mode
|
|
|
|
EP3CSetPrinterMode(g, data, control);
|
|
|
|
return rval;
|
|
}
|
|
|
|
//
|
|
// EP3CResetBus
|
|
//
|
|
// Resets the SCSI Bus
|
|
//
|
|
VOID EP3CResetBus(PADAPTER_INFO g)
|
|
{
|
|
UCHAR data;
|
|
UCHAR control;
|
|
|
|
// reset the EP3C
|
|
|
|
EP3CPortSet(g,EP3C_AREG2,EP3C_RST);
|
|
|
|
// put the parallel adapter into scsi mode
|
|
|
|
EP3CSetScsiMode(g, &data, &control);
|
|
|
|
// execute the complete command now, without interrupts
|
|
|
|
N53C400ResetBus(g);
|
|
|
|
// put the parallel adapter back to parallel mode
|
|
|
|
EP3CSetPrinterMode(g, data, control);
|
|
}
|
|
|
|
//
|
|
// N53C400PortPut
|
|
//
|
|
// This routine is used by the N53C400.C module to write byte to a 53C400
|
|
// controller. This allows the module to be card independent. Other
|
|
// modules that assume a N53C400 may also use this function.
|
|
//
|
|
VOID N53C400PortPut(PADAPTER_INFO g,UCHAR reg,UCHAR byte)
|
|
{
|
|
(*(g->EP3CWriteDataRegister))(g, reg, byte);
|
|
}
|
|
|
|
//
|
|
// N53C400PortGet
|
|
//
|
|
// This routine is used by the N53C400.C module to get a byte from a 53C400
|
|
// controller. This allows the module to be card independent. Other
|
|
// modules that assume a N53C400 may also use this function.
|
|
//
|
|
VOID N53C400PortGet(PADAPTER_INFO g,UCHAR reg,PUCHAR byte)
|
|
{
|
|
(*(g->EP3CReadDataRegister))(g, reg, byte);
|
|
}
|
|
|
|
//
|
|
// VOID N53C400PortSet
|
|
//
|
|
// Sets the bit pattern at the given register.
|
|
//
|
|
VOID N53C400PortSet(PADAPTER_INFO g,UCHAR reg,UCHAR byte)
|
|
{
|
|
UCHAR tmp;
|
|
(*(g->EP3CReadDataRegister))(g, reg, &tmp);
|
|
tmp |= byte;
|
|
(*(g->EP3CWriteDataRegister))(g, reg, tmp);
|
|
}
|
|
|
|
//
|
|
// VOID N53C400PortClear
|
|
//
|
|
// Clears a bit pattern at the given register.
|
|
//
|
|
VOID N53C400PortClear(PADAPTER_INFO g,UCHAR reg,UCHAR byte)
|
|
{
|
|
UCHAR tmp;
|
|
|
|
(*(g->EP3CReadDataRegister))(g, reg, &tmp);
|
|
tmp &= (byte ^ 0xff);
|
|
(*(g->EP3CWriteDataRegister))(g, reg, tmp);
|
|
}
|
|
|
|
//
|
|
// BOOLEAN N53C400PortTest
|
|
//
|
|
// Tests for a bit pattern on the given register.
|
|
//
|
|
BOOLEAN N53C400PortTest(PADAPTER_INFO g,UCHAR reg,UCHAR byte)
|
|
{
|
|
UCHAR tmp;
|
|
|
|
(*(g->EP3CReadDataRegister))(g, reg, &tmp);
|
|
return (tmp & byte);
|
|
}
|
|
|
|
|
|
//
|
|
// VOID N53C400PortGetBuffer
|
|
//
|
|
// Gets a buffer of 128 bytes from the n53c400. Note, the len here
|
|
// is ignored.
|
|
//
|
|
VOID N53C400PortGetBuffer(PADAPTER_INFO g, UCHAR reg,
|
|
PUCHAR pbytes, ULONG len)
|
|
{
|
|
// set the 53c400 register to access
|
|
|
|
(*(g->EP3CSetRegister))(g,reg);
|
|
|
|
// read the fifo
|
|
|
|
(*(g->EP3CReadFifo))(g->BaseIoAddress, pbytes);
|
|
}
|
|
|
|
//
|
|
// VOID N53C400PortPutBuffer
|
|
//
|
|
// Puts a buffer of 128 bytes from the n53c400. Note, the len here
|
|
// is ignored.
|
|
//
|
|
VOID N53C400PortPutBuffer(PADAPTER_INFO g, UCHAR reg,
|
|
PUCHAR pbytes, ULONG len)
|
|
{
|
|
// set the 53c400 register to access
|
|
|
|
(*(g->EP3CSetRegister))(g,reg);
|
|
|
|
// read the fifo
|
|
|
|
(*(g->EP3CWriteFifo))(g->BaseIoAddress, pbytes);
|
|
}
|
|
|
|
//======================================================================
|
|
// Conditionally-coded routines using in-line assembler.
|
|
//======================================================================
|
|
|
|
#ifdef WINNT
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// VOID EP3CReadFifoUniDir
|
|
//
|
|
// Reads bytes for uni-directional parallel port from the 53c400
|
|
// 128 byte buffer. The register must already be set the the
|
|
// 53c400 buffer register.
|
|
//
|
|
//----------------------------------------------------------------------
|
|
|
|
VOID EP3CReadFifoUniDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
|
|
{
|
|
_asm {
|
|
push ds
|
|
push edi
|
|
|
|
#ifdef MODE_32BIT
|
|
mov edi, pbytes
|
|
mov edx, baseIoAddress
|
|
#else
|
|
mov edi, word ptr pbytes
|
|
mov ds, word ptr pbytes+2
|
|
mov edx, word ptr baseIoAddress
|
|
#endif // MODE_32BIT
|
|
mov ecx, 128
|
|
loop0:
|
|
mov al, 0x80
|
|
out dx,al // select high nibble
|
|
|
|
jmp delay0
|
|
delay0:
|
|
|
|
add edx,2 // DX -> ctl reg
|
|
mov al,P_AFX // assert bufen and afx
|
|
out dx,al // assert dreg read
|
|
|
|
jmp delay1
|
|
delay1:
|
|
|
|
dec edx // DX -> stat reg
|
|
in al,dx // read high nibble
|
|
|
|
jmp delay2
|
|
delay2:
|
|
|
|
mov ah,al
|
|
shl ah,1
|
|
and ah,0f0h // AH -> adj high nibble
|
|
dec edx // DX -> data reg
|
|
sub al,al
|
|
out dx,al // select low nibble
|
|
|
|
jmp delay3
|
|
delay3:
|
|
|
|
inc edx // DX -> stat reg
|
|
in al,dx // read low nibble
|
|
|
|
shr al,1
|
|
shr al,1
|
|
shr al,1
|
|
and al,0fh // AL = adj low nibble
|
|
or al,ah // AL = recombined byte
|
|
|
|
mov [edi],al // store
|
|
inc edi // bump buf ptr
|
|
|
|
inc edx // DX -> ctl reg
|
|
xor al,al // negate afx (bufen stays asserted)
|
|
out dx,al // end read
|
|
|
|
jmp delay4
|
|
delay4:
|
|
|
|
sub edx,2 // DX -> data reg
|
|
dec ecx
|
|
jnz loop0
|
|
|
|
pop edi
|
|
pop ds
|
|
}
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
//
|
|
// VOID EP3CReadFifoUniDirSlow
|
|
//
|
|
// Reads bytes for uni-directional parallel port from the 53c400
|
|
// 128 byte buffer. The register must already be set the the
|
|
// 53c400 buffer register.
|
|
//
|
|
// USES FULL HANDSHAKING
|
|
//
|
|
//----------------------------------------------------------------------
|
|
|
|
VOID EP3CReadFifoUniDirSlow(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
|
|
{
|
|
_asm {
|
|
push ds
|
|
push edi
|
|
|
|
#ifdef MODE_32BIT
|
|
mov edi, pbytes
|
|
mov edx, baseIoAddress
|
|
#else
|
|
mov edi, word ptr pbytes
|
|
mov ds, word ptr pbytes+2
|
|
mov edx, word ptr baseIoAddress
|
|
#endif // MODE_32BIT
|
|
inc edx // edx - status register
|
|
mov ecx, 128
|
|
loop0:
|
|
|
|
dec edx // edx - data register
|
|
mov al, 0x80
|
|
out dx,al // select high nibble
|
|
|
|
jmp delay0
|
|
delay0:
|
|
|
|
add edx,2 // DX -> ctl reg
|
|
mov al,P_AFX // assert bufen and afx
|
|
out dx,al // assert dreg read
|
|
|
|
// wait till ready, P_BUSY asserted
|
|
dec edx // edx - status register
|
|
loop1:
|
|
in al,dx
|
|
test al, P_BUSY
|
|
jnz loop1
|
|
|
|
// delay to make sure we get high nibble in
|
|
jmp delay01
|
|
delay01:
|
|
in al,dx
|
|
|
|
mov ah,al
|
|
shl ah,1
|
|
and ah,0f0h // AH -> adj high nibble
|
|
dec edx // DX -> data reg
|
|
sub al,al
|
|
out dx,al // select low nibble
|
|
|
|
jmp delay3
|
|
delay3:
|
|
|
|
inc edx // DX -> stat reg
|
|
in al,dx // read low nibble
|
|
|
|
shr al,1
|
|
shr al,1
|
|
shr al,1
|
|
and al,0fh // AL = adj low nibble
|
|
or al,ah // AL = recombined byte
|
|
|
|
mov [edi],al // store
|
|
inc edi // bump buf ptr
|
|
|
|
inc edx // DX -> ctl reg
|
|
xor al,al // negate afx (bufen stays asserted)
|
|
out dx,al // end read
|
|
|
|
dec edx // DX -> status register
|
|
// wait for P_BUSY deasserted
|
|
loop2:
|
|
in al,dx
|
|
test al, P_BUSY
|
|
jz loop2
|
|
|
|
dec ecx
|
|
jnz loop0
|
|
|
|
pop edi
|
|
pop ds
|
|
}
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
//
|
|
// VOID EP3CReadFifoBiDir
|
|
//
|
|
// Reads bytes for bi-directional parallel port from the 53c400
|
|
// 128 byte buffer. The register must already be set the the
|
|
// 53c400 buffer register.
|
|
//
|
|
//----------------------------------------------------------------------
|
|
|
|
VOID EP3CReadFifoBiDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
|
|
{
|
|
_asm {
|
|
push ds
|
|
push edi
|
|
|
|
#ifdef MODE_32BIT
|
|
mov edi,pbytes
|
|
mov edx, baseIoAddress
|
|
#else
|
|
mov edi, word ptr pbytes
|
|
mov ds, word ptr pbytes+2
|
|
mov edx, word ptr baseIoAddress
|
|
#endif // MODE_32BIT
|
|
mov ecx, 128
|
|
add edx, 2 // edx - control register
|
|
loop0:
|
|
mov al, P_BUFEN + P_AFX
|
|
out dx, al
|
|
|
|
jmp delay0
|
|
delay0:
|
|
|
|
sub edx,2 // edx - data register
|
|
|
|
in al,dx
|
|
mov [edi], al
|
|
inc edi
|
|
|
|
add edx,2 // edx - control register
|
|
|
|
mov al, P_BUFEN
|
|
out dx, al
|
|
|
|
jmp delay1 // is this needed, there is a loop?
|
|
delay1:
|
|
|
|
dec ecx
|
|
jnz loop0
|
|
|
|
xor al,al // leave control regiser 0'd
|
|
out dx, al
|
|
|
|
pop edi
|
|
pop ds
|
|
}
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
//
|
|
// VOID EP3CReadFifoBiDirSlow
|
|
//
|
|
// Reads bytes for bi-directional parallel port from the 53c400
|
|
// 128 byte buffer. The register must already be set the the
|
|
// 53c400 buffer register.
|
|
//
|
|
// USES FULL HANDSHAKING
|
|
//
|
|
//----------------------------------------------------------------------
|
|
|
|
VOID EP3CReadFifoBiDirSlow(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
|
|
{
|
|
_asm {
|
|
push ds
|
|
push edi
|
|
|
|
#ifdef MODE_32BIT
|
|
mov edi,pbytes
|
|
mov edx, baseIoAddress
|
|
#else
|
|
mov edi, word ptr pbytes
|
|
mov ds, word ptr pbytes+2
|
|
mov edx, word ptr baseIoAddress
|
|
#endif // MODE_32BIT
|
|
mov ecx, 128
|
|
add edx, 0x02 // edx - control register
|
|
|
|
// wait for data to be ready, P_BUSY asserted
|
|
loop0:
|
|
mov al, P_BUFEN + P_AFX
|
|
out dx, al
|
|
|
|
dec edx // edx - status register
|
|
loop1:
|
|
in al,dx
|
|
test al, P_BUSY
|
|
jnz loop1
|
|
|
|
dec edx // edx - data register
|
|
|
|
in al,dx
|
|
mov [edi], al
|
|
inc edi
|
|
|
|
add edx,2 // edx - control register
|
|
|
|
// end data read cycle
|
|
mov al, P_BUFEN
|
|
out dx, al
|
|
|
|
dec edx // edx - status register
|
|
|
|
// wait for P_BUSY deasserted
|
|
loop2:
|
|
in al,dx
|
|
test al, P_BUSY
|
|
jz loop2
|
|
|
|
inc edx // edx - control register
|
|
|
|
dec ecx
|
|
jnz loop0
|
|
|
|
xor al,al // leave control regiser 0'd
|
|
out dx, al
|
|
|
|
pop edi
|
|
pop ds
|
|
}
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
//
|
|
// VOID EP3CWriteFifoUniDir
|
|
//
|
|
// Writes bytes thru uni-directional parallel port to the 53c400
|
|
// 128 byte buffer. The register must already be set the the
|
|
// 53c400 buffer register.
|
|
//
|
|
//----------------------------------------------------------------------
|
|
|
|
VOID EP3CWriteFifoUniDir(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
|
|
{
|
|
_asm {
|
|
push ds
|
|
push edi
|
|
|
|
#ifdef MODE_32BIT
|
|
mov edi,pbytes
|
|
mov edx, baseIoAddress
|
|
#else
|
|
mov edi, word ptr pbytes
|
|
mov ds, word ptr pbytes+2
|
|
mov edx, word ptr baseIoAddress
|
|
#endif // MODE_32BIT
|
|
mov ecx, 128
|
|
|
|
loop0:
|
|
mov al,[edi]
|
|
out dx,al
|
|
inc edi
|
|
|
|
add edx,2 ;DX -> ctl reg
|
|
mov al,P_STB ;assert bufen, stb
|
|
out dx,al
|
|
or al,P_AFX ;assert dreg write
|
|
out dx,al
|
|
|
|
jmp delay0
|
|
delay0:
|
|
;leave bufen asserted
|
|
mov al,0 ; and negate afx, stb
|
|
out dx,al ;end write
|
|
|
|
jmp delay1
|
|
delay1:
|
|
|
|
sub edx,2 ;DX -> data reg
|
|
dec ecx
|
|
jnz loop0
|
|
|
|
// let's leave control register 0'd for all these fifo routines...
|
|
// add edx,2 ;DX -> ctl reg
|
|
// or al,P_BUFEN ;negate bufen
|
|
// out dx,al
|
|
|
|
|
|
jmp delay2
|
|
delay2:
|
|
|
|
pop edi
|
|
pop ds
|
|
}
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
//
|
|
// VOID EP3CWriteFifoUniDirSlow
|
|
//
|
|
// Writes bytes thru uni-directional parallel port to the 53c400
|
|
// 128 byte buffer. The register must already be set the the
|
|
// 53c400 buffer register.
|
|
//
|
|
// USES FULL HANDSHAKING
|
|
//
|
|
//----------------------------------------------------------------------
|
|
|
|
VOID EP3CWriteFifoUniDirSlow(PBASE_REGISTER baseIoAddress, PUCHAR pbytes)
|
|
{
|
|
_asm {
|
|
push ds
|
|
push edi
|
|
|
|
#ifdef MODE_32BIT
|
|
mov edi,pbytes
|
|
mov edx, baseIoAddress
|
|
#else
|
|
mov edi, word ptr pbytes
|
|
mov ds, word ptr pbytes+2
|
|
mov edx, word ptr baseIoAddress
|
|
#endif // MODE_32BIT
|
|
mov ecx, 128
|
|
|
|
loop0:
|
|
mov al,[edi]
|
|
out dx,al
|
|
inc edi
|
|
|
|
add edx,2 ;DX -> ctl reg
|
|
mov al,P_STB ;assert bufen, stb
|
|
out dx,al
|
|
or al,P_AFX ;assert dreg write
|
|
out dx,al
|
|
|
|
// wait till ready, P_BUSY asserted
|
|
dec edx // edx - status register
|
|
loop1:
|
|
in al,dx
|
|
test al, P_BUSY
|
|
jnz loop1
|
|
|
|
inc edx // edx - control register
|
|
|
|
;leave bufen asserted
|
|
mov al,0 ; and negate afx, stb
|
|
out dx,al ;end write
|
|
|
|
dec edx // edx - status register
|
|
|
|
// wait for P_BUSY deasserted
|
|
loop2:
|
|
in al,dx
|
|
test al, P_BUSY
|
|
jz loop2
|
|
|
|
dec edx // edx - data register
|
|
|
|
dec ecx
|
|
jnz loop0
|
|
|
|
// let's leave control register 0'd for all these fifo routines...
|
|
// add edx,2 ;DX -> ctl reg
|
|
// or al,P_BUFEN ;negate bufen
|
|
// out dx,al
|
|
|
|
pop edi
|
|
pop ds
|
|
}
|
|
}
|
|
|
|
#endif // #ifdef WINNT
|