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376 lines
8.7 KiB
376 lines
8.7 KiB
#ifndef _MYDEFS_
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#define _MYDEFS_
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//
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// maximum number of idd's per adapter
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// this is one pcimac/4 adapter
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//
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#define MAX_IDD_PER_ADAPTER 4
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//
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// maximum number of conection objects per adapter
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// this is one for each bchannel of a pcimac/4
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//
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#define MAX_CM_PER_ADAPTER 8
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// maximum number of mtl objects per adapter
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// this is one for each bchannel of a pcimac/4
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//
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#define MAX_MTL_PER_ADAPTER 8
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//
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// number of adapters in system
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//
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#define MAX_ADAPTERS_IN_SYSTEM 8
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//
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// maximum number of idd's in system
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// this is 5 pcimac/4 adapters
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//
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#define MAX_IDD_IN_SYSTEM 20
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//
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// maximum number of connection objects
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// in system
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// this is 5 pcimac/4 adpaters with a
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// connection object for each bchannel
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//
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#define MAX_CM_IN_SYSTEM 40
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//
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// maximum number of mtl objects
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// in system
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// this is 5 pcimac/4 adpaters with a
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// connection object for each bchannel
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//
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#define MAX_MTL_IN_SYSTEM 40
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//
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// maximum number of cm channel objects
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// in system
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// this is 5 pcimac/4 adpaters with a
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// connection object for each bchannel
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//
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#define MAX_CHAN_IN_SYSTEM 40
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//
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// maximum number of calls that can be made on
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// single line
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//
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//#define MAX_CALL_PER_LINE 2
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#define MAX_CALL_PER_LINE 1
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//
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// maximum number of channels supported by an idd
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//
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#define MAX_CHANNELS_PER_IDD 2
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//
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// maximum number of channels supported by an idd
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//
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#define MAX_LTERMS_PER_IDD 2
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#define MAX_WANPACKET_XMITS 3
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#define MAX_WANPACKET_BUFFERSIZE 1500
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#define MAX_WANPACKET_HEADERPADDING 14
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#define MAX_WANPACKET_TAILPADDING 0
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//
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// connection data type's
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//
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#define CM_PPP 0
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#define CM_DKF 1
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//
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// maximum number of channels allowed in a single connection
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//
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#define MAX_CHAN_PER_CONN 8
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//
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// defines for adapter boardtypes
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//
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#define IDD_BT_PCIMAC 0 /* - ISA, single channel */
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#define IDD_BT_PCIMAC4 1 /* - ISA, four channel */
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#define IDD_BT_MCIMAC 2 /* - MCA, single channel */
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#define IDD_BT_DATAFIREU 3 /* - ISA/U, single channel */
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#define IDD_BT_DATAFIREST 4 /* - ISA/ST, single channel */
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#define IDD_BT_DATAFIRE4ST 5 /* - ISA/ST, four channel */
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//
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// Send window size
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//
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#define ISDN_WINDOW_SIZE 10
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//
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// Ndis Version Info
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//
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#define NDIS_MAJOR_VER 0x03
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#define NDIS_MINOR_VER 0x00
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//
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// OID Switch
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//
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#define OID_GEN_INFO 0x00000000
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#define OID_8023_INFO 0x01000000
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#define OID_WAN_INFO 0x04000000
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#define OID_TAPI_INFO 0x07000000
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//
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// idd polling timer value
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//
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#define IDD_POLL_T 25 // 25ms polling frequency (msec)
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//
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// cm polling timer
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//
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#define CM_POLL_T 1000 /* 1 second timer */
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//
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// mtl polling timer
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//
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#define MTL_POLL_T 25 // 25 ms timer
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//
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// flag to indicate this is not a beginning buffer
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//
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#define H_TX_N_BEG 0x8000
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#define H_RX_N_BEG 0x8000
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//
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// flag to indicate this is not an ending buffer
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//
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#define H_TX_N_END 0x4000
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#define H_RX_N_END 0x4000
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//
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// flag to cause an immediate send of queued tx buffers
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//
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#define H_TX_FLUSH 0x2000
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//
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// masks off tx flags to leave the tx length
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//
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#define H_TX_LEN_MASK 0x01FF
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#define H_RX_LEN_MASK 0x01FF
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//
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// mask off length leaving rx flags
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//
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#define RX_FLAG_MASK 0xF000
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//
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// mask off length and fragment indicator leaving tx flags
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//
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#define TX_FLAG_MASK 0xE000
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//
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// indicator that this tx is actually a fragment
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//
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#define TX_FRAG_INDICATOR 0x1000
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//
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// states for receive ppp state machine
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//
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#define RX_BEGIN 0
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#define RX_MIDDLE 1
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#define RX_END 2
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#ifdef DBG
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//
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// states for tx ppp state machine
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//
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#define TX_BEGIN 0
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#define TX_MIDDLE 1
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#define TX_END 2
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#endif
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//
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// idp tx and rx lengths
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//
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#define IDP_MAX_TX_LEN 280
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#define IDP_MAX_RX_LEN 280
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//
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// Idd frame type defines
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//
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#define IDD_FRAME_PPP 1 /* raw hdlc frames */
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#define IDD_FRAME_DKF 2 /* dror encapsulated frames */
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#define IDD_FRAME_DONTCARE 4 /* No data can pass yet */
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#define IDD_FRAME_DETECT 8 /* detect bchannel framing */
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//
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// ADP Stuff
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//
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//
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// ADP Register Defines
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//
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#define ADP_REG_ID 0
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#define ADP_REG_CTRL 1
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#define ADP_REG_ADDR_LO 2
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#define ADP_REG_ADDR_MID 3
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#define ADP_REG_ADDR_HI 4
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#define ADP_REG_DATA 5
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#define ADP_REG_DATA_INC 6
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#define ADP_REG_RESERVE1 7 // Currently unused.
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#define ADP_REG_ADAPTER_CTRL 8
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//
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// ADP_REG_ID Bits
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//
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#define ADP_BT_ADP1 0xA1
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#define ADP_BT_ADP4 0xA4
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//
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// ADP_REG_CTRL Bits
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//
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#define ADP_RESET_BIT 0x80 // R/W 1 - Holds Adapter in reset
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#define ADP_PIRQ_BIT 0x40 // R 1 - Adapter to PC Interrupt Active
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// W 1 - Clear Adapter to PC Interrupt
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#define ADP_AIRQ_BIT 0x20 // W 1 - PC to Adapter Interrupt Active
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// R 0 - PC to Adapter Interrupt seen
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#define ADP_HLT_BIT 0x10 // R/W 1 - Holds Adapter in halt
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#define ADP_PIRQEN_BIT 0x08 // R/W 1 - Enables Adapter to PC Interrupt
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#define ADP_INT_SEL_BITS 0x07 // R/W Adapter to PC Interrupt select
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// Code IRQ
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// 000 0 (Disabled)
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// 001 3
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// 010 5
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// 011 7
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// 100 10
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// 101 11
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// 110 12
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// 111 15
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//
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// ADP_REG_ADDR_LO Bits
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//
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// R/W Adapter Memory Address Bits A0..A7
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//
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// ADP_REG_ADDR_MID Bits
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//
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// R/W Adapter Memory Address Bits A8..A15
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//
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// ADP_REG_ADDR_HI Bits
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//
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// R/W Adapter Memory Address Bits A16..A23
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//
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// ADP_REG_DATA Bits
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//
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// R/W Adapter Memory Data Bits D0..D7
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// The 24 bit adapter memory address pointer remains constant
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// after each access to the data register.
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//
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// ADP_REG_DATA_INC Bits
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//
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// R/W Adapter Memory Data Bits D0..D7
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// The 24 bit adapter memory address pointer increments by one
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// after each access to the data register.
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//
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// ADP_REG_ADAPTER_CTRL Bits
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//
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// The Adapter Control Register is used by the host to determine IRQL
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// status and select a specific channel.
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//
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#define ADP_CSEL_BITS 0x03 // R/W Channel select bits
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// 00 - select channel 0
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// 01 - select channel 1
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// 10 - select channel 2
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// 11 - select channel 3
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#define ADP_ADAPTER_PIRQL 0xF0 // R replica of the IRQ lines from all
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// four channel. They are provided
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// for quick reference and can only
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// be cleared by accessing the Channel
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// Control Register.
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//
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// Maxium Adapter RAM Size
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//
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#define ADP_RAM_SIZE 0x40000L
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//
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// Offset to message to PC pending status windows
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//
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#define ADP_STS_WINDOW 0x500L
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//
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// Offset to PC to adapter command window
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//
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#define ADP_CMD_WINDOW 0x510L
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//
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// Offset to adapter enviornment window
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//
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#define ADP_ENV_WINDOW 0x540L
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//
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// Offset to adapter NVRAM window (copy in adapter memory)
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//
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#define ADP_NVRAM_WINDOW 0x940L
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//
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// some Adp bin file stuff
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//
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#define ADP_BIN_BLOCK_SIZE 256
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#define ADP_BIN_FORMAT 1
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//
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// Adp Status
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//
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typedef struct
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{
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UCHAR ReceiveStatus; // 0
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UCHAR Reserved1; // 1
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UCHAR MajorVersion; // 2
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UCHAR MinorVersion; // 3
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ULONG HeartBeat; // 4
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ULONG IdleCount; // 8
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USHORT AbortReason; // 12
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USHORT SpuriousInterrupt; // 14
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} ADP_STATUS;
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//
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// Adp bin file header
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//
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typedef struct
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{
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USHORT Format;
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USHORT BlockCount;
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ULONG ImageSize;
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}ADP_BIN_HEADER;
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//
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// Adp bin file data block
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//
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typedef struct
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{
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ULONG Address;
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UCHAR Data[ADP_BIN_BLOCK_SIZE];
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}ADP_BIN_BLOCK;
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//
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// NVRAM stuff
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//
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#define ADP_NVRAM_MAX 64
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typedef struct
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{
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USHORT NVRamImage[ADP_NVRAM_MAX];
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}ADP_NVRAM;
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//
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// IDP Stuff
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//
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#define IDP_STS_WINDOW 0x800
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#define IDP_CMD_WINDOW 0x810
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#define IDP_ENV_WINDOW 0x910
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#define IDP_RAM_PAGE_SIZE 0x4000
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#endif /* _MYTYPES_ */
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