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234 lines
14 KiB
234 lines
14 KiB
/****************************************************************************/
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/****************************************************************************/
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/* */
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/* THE MADGE ADAPTER CARD DEFINITIONS (ATULA CARDS) */
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/* ================================================ */
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/* */
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/* FTK_AT.H : Part of the FASTMAC TOOL-KIT (FTK) */
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/* */
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/* Copyright (c) Madge Networks Ltd. 1991-1994 */
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/* Developed by MF */
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/* CONFIDENTIAL */
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/* */
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/* */
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/****************************************************************************/
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/* */
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/* This header file contains the definitions for programming Madge ATULA */
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/* adapter cards. Each adapter card has a number of control and status */
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/* registers. ALL bits in ALL registers are defined by Madge Networks Ltd, */
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/* however only a restricted number are defined below as used within the */
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/* FTK. All other bits must NOT be changed and no support will be offered */
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/* for any application that does so or uses the defined bits in any way */
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/* different to the FTK. */
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/* */
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/* Note: The ATULA is Madge Network's name for the ASIC on its 16/4 AT and */
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/* 16/4 PC adapter cards. */
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/* */
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/****************************************************************************/
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/****************************************************************************/
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/* */
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/* VERSION_NUMBER of FTK to which this FTK_AT.H belongs : */
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/* */
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#define FTK_VERSION_NUMBER_FTK_AT_H 221
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/****************************************************************************/
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/* */
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/* Values : ATULA REGISTER MAP */
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/* */
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/* Madge 16/4 AT and 16/4 PC adapter cards both use the ATULA and hence */
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/* have the following register map. By setting certain bits in the control */
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/* registers it is possible to page in a) the status register or the PIO */
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/* address registers, b) the BIA PROM (page 0 or page 1) or the EAGLE SIF */
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/* registers (normal or extended). */
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/* */
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/* NB. There is a lot of similarity between the ATULA and MC register maps. */
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/* */
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#define ATULA_IO_RANGE 32
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#define ATULA_CONTROL_REGISTER_1 1
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#define ATULA_CONTROL_REGISTER_2 2
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#define ATULA_STATUS_REGISTER 3
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#define ATULA_CONTROL_REGISTER_6 6
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#define ATULA_CONTROL_REGISTER_7 7
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#define ATULA_FIRST_SIF_REGISTER 8
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#define ATULA_BIA_PROM 8
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#define ATULA_PIO_ADDRESS_LOW_REGISTER 3
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#define ATULA_PIO_ADDRESS_MID_REGISTER 4
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#define ATULA_PIO_ADDRESS_HIGH_REGISTER 5
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#define AT_P_EISA_REV2_CTRL_REG 21
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#define AT_P_SW_CONFIG_REG 22
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/****************************************************************************/
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/* */
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/* Values : ATULA CONTROL_REGISTER_1 */
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/* */
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/* These are the bit definitions for control register 1 on ATULA cards. */
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/* */
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/* NB. The bit definitions are mostly the same as MC CONTROL_REGISTER_1. */
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/* */
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#define ATULA_CTRL1_SINTREN ((BYTE) 0x01) /* SIF interrupt enable */
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#define ATULA_CTRL1_NSRESET ((BYTE) 0x04) /* active low SIF reset */
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#define ATULA_CTRL1_SRSX ((BYTE) 0x40) /* SIF extended register select */
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#define ATULA_CTRL1_4_16_SEL ((BYTE) 0x80) /* Select 4 or 16 Mb/s */
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/****************************************************************************/
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/* */
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/* Values : ATULA CONTROL_REGISTER_2 BITS */
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/* */
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/* These are the bit definitions for control register 2 on ATULA cards. */
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/* */
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#define ATULA_CTRL2_CS16DLY ((BYTE) 0x01) /* 1=REV3, 0=REV4 bus timings */
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#define ATULA_CTRL2_ADDSEL ((BYTE) 0x04) /* page in PIO addr regs (PIO) */
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#define ATULA_CTRL2_SHRQEN ((BYTE) 0x10) /* SHRQ enable (PIO) */
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#define ATULA_CTRL2_INTEN ((BYTE) 0x20) /* overall interrupt enable */
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#define ATULA_CTRL2_SHRQ ((BYTE) 0x40) /* SHRQ pin status (PIO) */
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#define ATULA_CTRL2_SHLDA ((BYTE) 0x80) /* SHLDA pin status (PIO) */
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/****************************************************************************/
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/* */
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/* Values : ATULA CONTROL_REGISTER_6 BITS */
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/* */
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/* These are the bit definitions for control register 6 on ATULA cards. */
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/* */
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#define ATULA_CTRL6_MODES ((BYTE) 0x03) /* transfer mode (2 bits) */
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#define ATULA_CTRL6_UDRQ ((BYTE) 0x04) /* user generate DMA request */
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#define ATULA_CTRL6_DMAEN ((BYTE) 0x08) /* enable DMA */
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#define ATULA_CTRL6_CLKSEL ((BYTE) 0xC0) /* clock speed select (2 bits) */
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/****************************************************************************/
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/* */
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/* Values : ATULA CONTROL_REGISTER_7 */
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/* */
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/* These are the bit definitions for control register 7 on ATULA cards. */
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/* */
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/* NB. The bit definitions are mostly the same as MC CONTROL_REGISTER_0. */
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/* */
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#define ATULA_CTRL7_SIFSEL ((BYTE) 0x04) /* page in BIA PROM or SIF regs */
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#define ATULA_CTRL7_PAGE ((BYTE) 0x08) /* pages BIA PROM or EEPROM */
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#define ATULA_CTRL7_UINT ((BYTE) 0x10) /* user generate interrupt */
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#define ATULA_CTRL7_SINTR ((BYTE) 0x40) /* SIF interrupt pending */
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#define ATULA_CTRL7_REV_4 ((BYTE) 0x80) /* 1=REV4, 0=REV3 mode */
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/****************************************************************************/
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/* */
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/* Values : ATULA STATUS_REGISTER BITS */
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/* */
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/* These are the bit definitions for the status register on ATULA cards. */
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/* */
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#define ATULA_STATUS_SDDIR ((BYTE) 0x10) /* data xfer direction (PIO) */
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#define ATULA_STATUS_ASYN_BUS ((BYTE) 0x20) /* asynchronous bus */
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#define ATULA_STATUS_BUS8 ((BYTE) 0x40) /* 8 bit slot */
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/****************************************************************************/
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/* */
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/* Values : MODE IN ATULA CONTROL_REGISTER_6 */
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/* */
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/* The two mode select bits in control register 6 (ATULA_CTRL6_MODES) are */
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/* configured for the data transfer mode being used. */
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/* */
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#define ATULA_CTRL6_MODE_BUS_MASTER ((BYTE) 0x03) /* bus master DMA mode */
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#define ATULA_CTRL6_MODE_PIO ((BYTE) 0x00) /* PIO mode */
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/****************************************************************************/
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/* */
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/* Values : CLOCK SPEED IN ATULA CONTROL_REGISTER_6 */
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/* */
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/* The two SIF clock speed select bits in control register 6 */
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/* (ATULA_CTRL6_CLKSEL) are configured for either on-board (8MHz) or host */
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/* oscillator frequency. */
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/* */
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#define ATULA_CTRL6_CLKSEL_HOST ((BYTE) 0xC0) /* host bus */
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#define ATULA_CTRL6_CLKSEL_ON_BOARD ((BYTE) 0x00) /* 8Mhz on board */
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/****************************************************************************/
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/* */
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/* Values : FIELDS IN THE AT_P_EISA_REV2_CTRL REGISTER */
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/* */
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/* These bit masks define bit fields within the AT/P control register. */
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/* */
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#define ATP_RSCTRL ((BYTE) 0x08)
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#define ATP_CLKDIV ((BYTE) 0x10)
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/****************************************************************************/
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/* */
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/* Values : FIELDS IN THE AT_P_SW_CONFIG REGISTER */
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/* */
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/* These bit masks define bit fields within the AT/P control register. */
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/* */
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#define ATP_INTSEL0 ((BYTE) 0x01)
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#define ATP_INTSEL1 ((BYTE) 0x02)
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#define ATP_INTSEL2 ((BYTE) 0x04)
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#define ATP_INTSEL ((BYTE) 0x07)
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#define ATP_DMA0 ((BYTE) 0x08)
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#define ATP_DMA1 ((BYTE) 0x10)
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#define ATP_DMA ((BYTE) 0x18)
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#define ATP_S4N16 ((BYTE) 0x40)
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/****************************************************************************/
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/* */
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/* Value : PIO IO LOCATION */
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/* */
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/* The IO location used during PIO for reading/writing data from/to the */
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/* adapter card is mapped on top of the EAGLE SIFDAT register in the ATULA */
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/* card register map. */
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/* */
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#define ATULA_PIO_IO_LOC 0
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/****************************************************************************/
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/* */
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/* Values : ATULA EXTENDED EAGLE SIF REGISTERS */
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/* */
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/* The EAGLE SIF registers are in two groups - the normal SIF registers */
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/* (those from the old TI chipset) and the extended SIF registers (those */
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/* particular to the EAGLE). For Madge ATULA adapter cards, with */
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/* CTRL7_SIFSEL = 1 and CTRL1_NRESET = 1, having CTRL1_SRSX = 0 selects the */
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/* normal SIF registers and having CTRL1_SRSX = 1 selects the extended SIF */
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/* registers. */
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/* */
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/* The definitions for the normal SIF registers are in FTK_CARD.H because */
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/* they appear in the same relative IO locations for all adapter cards. The */
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/* extended SIF registers are here because they appear at different */
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/* relative IO locations for different types of adapter cards. For ATULA */
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/* and MC cards they are in fact identical. */
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/* */
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#define ATULA_EAGLE_SIFACL 0 /* adapter control */
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#define ATULA_EAGLE_SIFADR_2 2 /* copy of SIFADR */
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#define ATULA_EAGLE_SIFADX 4 /* DIO address (high) */
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#define ATULA_EAGLE_DMALEN 6 /* DMA length */
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/* */
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/* */
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/************** End of FTK_AT.H file ****************************************/
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/* */
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/* */
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