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122 lines
6.5 KiB
122 lines
6.5 KiB
/****************************************************************************/
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/****************************************************************************/
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/* */
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/* THE MADGE ADAPTER CARD DEFINITIONS (PCI CARDS) */
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/* =================================================== */
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/* */
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/* FTK_PCI2.H : Part of the FASTMAC TOOL-KIT (FTK) */
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/* */
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/* Copyright (c) Madge Networks Ltd. 1994 */
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/* Developed by PRR */
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/* CONFIDENTIAL */
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/* */
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/* */
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/****************************************************************************/
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/* */
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/* This header file contains the definitions for programming Madge Smart */
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/* 16/4 PCI (BM) adapter cards, ie based on the Madge bus interface ASIC. */
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/* */
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/* The SIF registers are WORD aligned and start at offset 0x10 from the IO */
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/* space */
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/* */
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/****************************************************************************/
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/****************************************************************************/
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/* */
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/* VERSION_NUMBER of FTK to which this FTK_PCI.H belongs : */
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/* */
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#define FTK_VERSION_NUMBER_FTK_PCI_H 221
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/***************************************************************************/
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/* */
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/* PCI-2 IO Map */
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/* Offsets of register locations are from the start of the card's IO space.*/
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/* */
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#define PCI2_INTERRUPT_STATUS 0x01 /* One byte. */
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#define PCI2_DMAING 0x01 /* Bit 0 - Dma in progress */
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#define PCI2_SINTR 0x02 /* Bit 1 - SIF int */
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#define PCI2_SWINT 0x04 /* Bit 2 - Software int */
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#define PCI2_PCI_INT 0x80 /* Bit 8 - Catastrophic error */
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#define PCI2_INTERRUPT_CONTROL 0x02 /* One byte. */
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#define PCI2_SINTEN 0x02 /* Bit 1 - SIF int enable */
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#define PCI2_SWINTEN 0x04 /* Bit 2 - S/w int enable */
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#define PCI2_PCI_ERR_EN 0x80 /* Bit 9 - Catastrophic err en */
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#define PCI2_RESET 0x04 /* One byte. */
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#define PCI2_CHIP_NRES 0x01 /* Bit 0 - Reset chip if zero */
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#define PCI2_FIFO_NRES 0x02 /* Bit 2 - Fifo reset if zero */
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#define PCI2_SIF_NRES 0x04 /* Bit 3 - SIF reset if zero */
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#define PCI2_SEEPROM_CONTROL 0x07 /* One byte. */
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#define PCI2_SEESK 0x01 /* Bit 0 - Clock */
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#define PCI2_SEED 0x02 /* Bit 1 - Data */
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#define PCI2_SEEOE 0x04 /* Bit 2 - Output enable */
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#define PCI2_EEPROM_CONTROL 0x08 /* Dword - Low 19 bits are addr */
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#define PCI2_AUTOINC 0x80000000 /* Bit 31 - Does addr autoinc */
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#define PCI2_EEPROM_DATA 0x0C /* One byte. */
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#define PCI2_SIF_OFFSET 0x10
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/* Locations 0x22 onwards are for ASIC debugging only */
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#define PCI2_IO_RANGE 0x36
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/****************************************************************************/
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/* */
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/* Bits for programming the EEPROM */
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/* */
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/* */
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#define AT24_IO_CLOCK 1
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#define AT24_IO_DATA 2
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#define AT24_IO_ENABLE 4
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/****************************************************************************/
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/* */
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/* Usefule locations in the EEPROM */
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/* */
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/* */
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#define PCI2_EEPROM_BIA_WORD0 9
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#define PCI2_EEPROM_BIA_WORD1 10
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#define PCI2_EEPROM_BIA_WORD2 11
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#define PCI2_EEPROM_RING_SPEED 12
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#define PCI2_EEPROM_RAM_SIZE 13
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#define PCI2_HWF1 14
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#define PCI2_HWF2 15
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/****************************************************************************/
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/* */
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/* Useful values in the EEPROM */
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/* */
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#define PCI2_EEPROM_4MBITS 1
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#define PCI2_EEPROM_16MBITS 0
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#define PCI2_BUS_MASTER_ONLY 4
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#define PCI2_HW2_431_READY 0x10
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/****************************************************************************/
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/* */
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/* Useful locations in the PCI config space */
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/* */
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/* */
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#define PCI_CONFIG_COMMAND 0x4
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/****************************************************************************/
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/* */
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/* The BUS Master DMA Enable bit in the CONFIG_COMMAND register */
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#define PCI_CONFIG_BUS_MASTER_ENABLE 0x4
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/* */
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/* */
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/************** End of FTK_PCI.H file ***************************************/
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/* */
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/* */
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