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109 lines
5.8 KiB
109 lines
5.8 KiB
/****************************************************************************/
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/****************************************************************************/
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/* */
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/* THE MADGE ADAPTER CARD DEFINITIONS (PCI CARDS) */
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/* =================================================== */
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/* */
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/* FTK_PCIT.H : Part of the FASTMAC TOOL-KIT (FTK) */
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/* */
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/* Copyright (c) Madge Networks Ltd. 1994 */
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/* Developed by PRR */
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/* CONFIDENTIAL */
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/* */
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/* */
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/****************************************************************************/
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/* */
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/* This header file contains the definitions for programming Madge Smart */
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/* 16/4 PCI (T) adapter cards, ie based on the Ti PCI bus interface ASIC */
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/* The only IO registers are the SIF registers, all other control is */
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/* through PCI config space */
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/****************************************************************************/
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/****************************************************************************/
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/* */
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/* VERSION_NUMBER of FTK to which this FTK_PCI.H belongs : */
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/* */
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#define FTK_VERSION_NUMBER_FTK_PCI_H 221
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/****************************************************************************/
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/* */
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/* Values : PCI REGISTER MAP */
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/* */
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/* The Madge PCI Ringnode uses the following register layout. */
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/* N.B. The SIF registers are mapped linearly, with no overlaying. */
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/* */
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#define PCIT_HANDSHAKE 0x100C
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#define PCIT_HANDSHAKE 0x100C
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/****************************************************************************/
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/* */
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/* Useful locations in the PCI config space */
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/* */
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/* */
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#define EEPROM_OFFSET 0x48
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#define MISC_CONT_REG 0x40
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#define PCI_CONFIG_COMMAND 0x4
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#define CACHE_LINE_SIZE 0xC
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/****************************************************************************/
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/* */
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/* The BUS Master DMA Enable bit in the CONFIG_COMMAND register */
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#define PCI_CONFIG_BUS_MASTER_ENABLE 0x4
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#define PCI_CONFIG_IO_ENABLE 0x2
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#define PCI_CONFIG_MEM_ENABLE 0x1
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/****************************************************************************/
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/* */
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/* Bits for programming the EEPROM */
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/* */
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/* */
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#define AT24_IO_CLOCK 1
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#define AT24_IO_DATA 2
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#define AT24_IO_ENABLE 4
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/****************************************************************************/
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/* */
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/* EEPROM commands */
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/* */
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#define AT24_WRITE_CMD 0xA0
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#define AT24_READ_CMD 0xA1
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/****************************************************************************/
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/* */
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/* Useful locations in the EEPROM */
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/* */
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/* */
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#define PCIT_EEPROM_BIA_WORD0 9
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#define PCIT_EEPROM_BIA_WORD1 10
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#define PCIT_EEPROM_BIA_WORD2 11
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#define PCIT_EEPROM_RING_SPEED 12
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#define PCIT_EEPROM_RAM_SIZE 13
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#define PCIT_EEPROM_HWF2 15
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#define NSEL_4MBITS 3
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#define NSEL_16MBITS 1
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/****************************************************************************/
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/* */
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/* Values in the EEPROM */
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/* */
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#define PCIT_EEPROM_4MBITS 1
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#define PCIT_EEPROM_16MBITS 0
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#define PCIT_BROKEN_DMA 0x20
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/*
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* Value passed to the adapter in the mc32 byte to tell it to use the FMPLUS
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* code which supports broken DMA.
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*/
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#define TRN_PCIT_BROKEN_DMA 0x200
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/* */
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/* */
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/************** End of FTK_PCI.H file ***************************************/
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/* */
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/* */
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