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256 lines
14 KiB
256 lines
14 KiB
/****************************************************************************/
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/****************************************************************************/
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/* */
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/* THE MADGE ADAPTER CARD DEFINITIONS (PCMCIA CARDS) */
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/* ================================================= */
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/* */
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/* FTK_PCMC.H : Part of the FASTMAC TOOL-KIT (FTK) */
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/* */
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/* Copyright (c) Madge Networks Ltd. 1991-1994 */
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/* Developed by VL */
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/* CONFIDENTIAL */
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/* */
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/* */
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/****************************************************************************/
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/* */
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/* This header file contains the definitions for programming Madge PCMCIA */
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/* adapter cards. Each adapter card has a number of control and status */
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/* registers. ALL bits in ALL registers are defined by Madge Networks Ltd, */
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/* however only a restricted number are defined below as used within the */
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/* FTK. All other bits must NOT be changed and no support will be offered */
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/* for any application that does so or uses the defined bits in any way */
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/* different to the FTK. */
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/* */
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/****************************************************************************/
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/****************************************************************************/
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/* */
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/* VERSION_NUMBER of FTK to which this FTK_PCMC.H belongs : */
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/* */
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#define FTK_VERSION_NUMBER_FTK_PCMC_H 221
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/****************************************************************************/
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/* */
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/* Values : PCMCIA REGISTER MAP */
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/* */
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/* Madge PCMCIA cards have the following register map. All SIF registers */
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/* are always visible. */
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/* */
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#define PCMCIA_IO_RANGE 32
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#define PCMCIA_CONTROL_REGISTER_1 0x0000
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#define PCMCIA_CONTROL_REGISTER_2 0x0002
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#define PCMCIA_PIO_IO_LOC 0x0008
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#define PCMCIA_FIRST_SIF_REGISTER 0x0010
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/****************************************************************************/
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/* */
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/* Values : PCMCIA_CONTROL_REGISTER_1 */
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/* */
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/* These are bit definitions for control register 1 on PCMCIA adapters. */
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/* */
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#define PCMCIA_CTRL1_SINTREN ((BYTE) 0x01) /* SIF interrupt enable */
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#define PCMCIA_CTRL1_SRESET ((BYTE) 0x02) /* EAGLE SIF reset */
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#define PCMCIA_CTRL1_CISDIS ((BYTE) 0x04) /* CIS ROM / extern EEPROM */
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#define PCMCIA_CTRL1_SHLDA ((BYTE) 0x40) /* SHLDA pin status (PIO) */
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#define PCMCIA_CTRL1_SHRQ ((BYTE) 0x80) /* SHRQ pin status (PIO) */
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/****************************************************************************/
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/* */
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/* Values : PCMCIA_CONTROL_REGISTER_2 */
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/* */
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/* These are bit definitions for control register 2 on PCMCIA adapters. */
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/* */
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#define PCMCIA_CTRL2_SBCKSEL ((BYTE) 0x03) /* SIF clock frequency */
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#define PCMCIA_CTRL2_4N16 ((BYTE) 0x04) /* Ring speed 4/16 */
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#define PCMCIA_CTRL2_FLSHWREN ((BYTE) 0x08) /* EEPROM write enable */
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#define PCMCIA_CTRL2_E2SK ((BYTE) 0x10) /* SK (sync clk) pin of EEPROM */
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#define PCMCIA_CTRL2_E2CS ((BYTE) 0x20) /* CS (chip sel) pin of EEPROM */
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#define PCMCIA_CTRL2_E2DI ((BYTE) 0x40) /* DI (data in) pin of EEPROM */
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#define PCMCIA_CTRL2_E2DO ((BYTE) 0x80) /* Output statue of EEPROm */
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#define PCMCIA_CTRL2_4N16_4 ((BYTE) 0x04) /* ringspeed = 4MB/s */
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#define PCMCIA_CTRL2_4N16_16 ((BYTE) 0x00) /* ringspeed = 16MB/s */
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#define PCMCIA_CTRL2_SBCKSEL_2 ((BYTE) 0x00) /* sif clock frequency 2MHz */
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#define PCMCIA_CTRL2_SBCKSEL_8 ((BYTE) 0x01) /* sif clock frequency 8MHz */
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#define PCMCIA_CTRL2_SBCKSEL_16 ((BYTE) 0x02) /* sif clock frequency 16MHz */
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#define PCMCIA_CTRL2_SBCKSEL_32 ((BYTE) 0x03) /* sif clock frequency 32MHz */
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/****************************************************************************/
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/* */
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/* Values : PCMCIA EXTENDED EAGLE SIF REGISTERS */
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/* */
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/* The EAGLE SIF registers are in two groups - the normal SIF registers */
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/* (those from the old TI chipset) and the extended SIF registers (those */
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/* particular to the EAGLE). For Madge PCMCIA adapter cards, both normal */
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/* and extended SIF registers are always accessible. */
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/* */
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/* The definitions for the normal SIF registers are in FTK_CARD.H because */
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/* they appear in the same relative IO locations for all adapter cards. The */
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/* extended SIF registers are here because they appear at different */
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/* relative IO locations for different types of adapter cards. */
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/* */
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#define PCMCIA_EAGLE_SIFACL 8 /* adapter control */
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#define PCMCIA_EAGLE_SIFADR_2 10 /* copy of SIFADR */
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#define PCMCIA_EAGLE_SIFADX 12 /* DIO address (high) */
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#define PCMCIA_EAGLE_DMALEN 14 /* DMA length */
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/****************************************************************************/
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/* */
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/* Values : PCMCIA CARD CONFIGURATION REGISTER */
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/* */
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/* These are definition of PCMCIA card configuration register (CCR) which */
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/* are mapped into attribute memory space. They should only be accessed */
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/* through PCMCIA Card Services. */
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/* */
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#define PCMCIA_CONFIG_BASE 0x00000800 /* Offset from attribute memory space */
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/* SMART 16/4 PCMCIA ringnode only have Configuration Option Register and */
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/* Configuration Status Register. There are no Pin Register and Socket/Copy */
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/* Register. */
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#define PCMCIA_REGISTER_PRESENT RC_PRESENT_OPTION_REG | RC_PRESENT_STATUS_REG
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#define PCMCIA_OPTION_REG 0x00 /* configruation option register (COR) */
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#define PCMCIA_STATUS_REG 0x02 /* configuration status register (CSR) */
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/****************************************************************************/
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/* */
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/* Values : PCMCIA CARD CONFIGURATION OPTION REGISTER (COR) */
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/* */
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#define PCMCIA_COR_CNFGD_MASK ((BYTE) 0x3F) /* IO Config. Enable port */
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#define PCMCIA_COR_LEVLREQ ((BYTE) 0x40) /* Level/Edge IRQ mode select */
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#define PCMCIA_COR_SYSRESET ((BYTE) 0x80) /* soft reset (not sif reset) */
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/****************************************************************************/
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/* */
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/* Values : PCMCIA CARD CONFIGURATION STATUS REGISTER (CSR) */
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/* */
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#define PCMCIA_CSR_RSRVD2 ((BYTE) 0x01) /* Reserved */
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#define PCMCIA_CSR_INTR ((BYTE) 0x02) /* Interrupt request to host */
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#define PCMCIA_CSR_PWRDWN ((BYTE) 0x04) /* Power down bit. Not used */
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#define PCMCIA_CSR_AUDIO ((BYTE) 0x08) /* Audio. Not used */
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#define PCMCIA_CSR_RSRVD1 ((BYTE) 0x10) /* Reserved */
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#define PCMCIA_CSR_IOIS8 ((BYTE) 0x20) /* 8-bit/16-bit data path */
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#define PCMCIA_CSR_SIGCHG ((BYTE) 0x40) /* Status Change. Not used */
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#define PCMCIA_CSR_CHANGED ((BYTE) 0x80) /* Not used */
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/****************************************************************************/
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/* */
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/* Initial Setting of these register */
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/* */
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#define PCMCIA_STATUS_REG_SETTING ((BYTE) 0x00)
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#define PCMCIA_PIN_REG_SETTING ((BYTE) 0x00)
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#define PCMCIA_COPY_REG_SETTING ((BYTE) 0x00)
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#define PCMCIA_OPTION_REG_SETTING \
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( 0x01 & PCMCIA_COR_CNFGD_MASK ) | PCMCIA_COR_LEVLREQ
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/****************************************************************************/
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/* */
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/* Other Hardware specification related definitions */
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/* */
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/* */
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/* EEPROM */
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/* */
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#define C46_START_BIT 0x8000 /* start bit of command */
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#define C46_READ_CMD 0x4000 /* command to enable reading of EEPROM */
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#define C46_ADDR_MASK 0x003F /* Bottom 6 bits are the address */
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#define C46_ADDR_SHIFT 7 /* no. of bits to shift the address */
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#define C46_CMD_LENGTH 9 /* 1 start bit, 2 cmd bits, 6 adr bits */
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#define EEPROM_ADDR_NODEADDR1 0x0000 /* 1st word in EEPROM = Nodeaddress1 */
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#define EEPROM_ADDR_NODEADDR2 0x0001 /* 2nd word in EEPROM = Nodeaddress2 */
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#define EEPROM_ADDR_NODEADDR3 0x0002 /* 3rd word in EEPROM = Nodeaddress3 */
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#define EEPROM_ADDR_RINGSPEED 0x0003 /* 4th word in EEPROM = RingSpeed */
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#define EEPROM_ADDR_RAMSIZE 0x0004 /* 5th word in EEPROM = Ram size / 128 */
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#define EEPROM_ADDR_REVISION 0x0005 /* 6th word in EEPROM = Revsion */
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#define EEPROM_RINGSPEED_16 0x0000 /* The 4th word = 0 -> 16MB/s */
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#define EEPROM_RINGSPEED_4 0x0001 /* The 4th word = 1 -> 4MB/s */
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/* */
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/* Miscellaneous */
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/* */
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#define PCMCIA_RAM_SIZE 512 /* 512k RAM on adapter */
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#define PCMCIA_NUMBER_OF_ADDR_LINES 16 /* Number of address lines decoded */
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#define PCMCIA_VCC 50 /* Vcc in tenth of a volt */
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#define PCMCIA_VPP1 0 /* Vpp1 in tenth of a volt */
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#define PCMCIA_VPP2 0 /* Vpp2 in tenth of a volt */
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/****************************************************************************/
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/* */
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/* Madge Signature for tuple CISTPL_VERS_1 */
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/* */
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#define MADGE_TPLLV1_INFO_LEN 33 /* note that there is a '\0' in the string */
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/* so strlen will not work. */
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/* 123456 789012345678901234567890123 */
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#define MADGE_TPLLV1_INFO_STRING "MADGE\0SMART 16/4 PCMCIA RINGNODE"
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/****************************************************************************/
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/* */
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/* Data sturcture of tuple CISTPL_VERS_1 */
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/* */
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/* Note that CS Level 2.00 or below start with a byte of tpl_code and a */
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/* byte of tpl_link. They are removed in CS Level 2.01 */
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/* */
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struct STRUCT_CS200_CISTPL_VERS_1_DATA
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{
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BYTE tpl_code;
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BYTE tpl_link;
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BYTE tpllv1_major;
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BYTE tpllv1_minor;
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BYTE info[MADGE_TPLLV1_INFO_LEN];
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BYTE additional_info[1];
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};
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typedef struct STRUCT_CS200_CISTPL_VERS_1_DATA CS200_CISTPL_VERS_1_DATA;
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struct STRUCT_CS201_CISTPL_VERS_1_DATA
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{
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BYTE tpllv1_major;
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BYTE tpllv1_minor;
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BYTE info[MADGE_TPLLV1_INFO_LEN];
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BYTE additional_info[1];
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};
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typedef struct STRUCT_CS201_CISTPL_VERS_1_DATA CS201_CISTPL_VERS_1_DATA;
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/* */
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/* */
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/********************* End of FTK_PCMC.H file *****************************/
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/* */
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/* */
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