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142 lines
6.4 KiB
142 lines
6.4 KiB
/****************************************************************************/
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/****************************************************************************/
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/* */
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/* THE MADGE ADAPTER CARD DEFINITIONS (Plug aNd Play (PNP) CARDS) */
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/* ============================================================== */
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/* */
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/* FTK_PNP.H : Part of the FASTMAC TOOL-KIT (FTK) */
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/* */
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/* Copyright (c) Madge Networks Ltd. 1991-1994 */
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/* Developed by AC */
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/* CONFIDENTIAL */
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/* */
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/* */
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/****************************************************************************/
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/* */
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/* This header file contains the definitions for programming Madge PNP */
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/* adapter cards. These adapter cards have a couple of control registers, */
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/* in addition to the SIF registers. ALL bits in ALL control registers are */
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/* defined by Madge Networks Ltd */
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/* */
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/****************************************************************************/
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/****************************************************************************/
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/* */
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/* VERSION_NUMBER of FTK to which this FTK_PNP.H belongs : */
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/* */
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#define FTK_VERSION_NUMBER_FTK_PNP_H 221
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/****************************************************************************/
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/* */
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/* Values : PNP REGISTER MAP */
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/* */
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/* The Madge Smart 16 Ringnode uses the following register layout. */
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/* N.B. The SIF registers are mapped linearly, with no overlaying. */
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/* */
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#define PNP_IO_RANGE 32
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#define PNP_CONTROL_REGISTER_1 3
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#define PNP_ID_REGISTER 8
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#define PNP_FIRST_SIF_REGISTER 16
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/****************************************************************************/
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/* */
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/* Values : PNP CONFIGURATION REGISTERS */
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/* */
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/* These are the bit definitions for the PnP configuration registers. */
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/* */
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#define PNP_CONFIG_ADDRESS_REGISTER 1
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#define PNP_CONFIG_DATA_REGISTER 2
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#define PNP_VENDOR_CONFIG_BYTE ((BYTE) 0xf0)
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#define PNP_VENDOR_CONFIG_IRQ ((BYTE )0x70)
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#define PNP_VENDOR_CONFIG_4MBITS ((BYTE) 0x80)
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#define PNP_VENDOR_CONFIG_RSVALID ((BYTE) 0x02)
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#define PNP_VENDOR_CONFIG_PXTAL ((BYTE) 0x01)
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/****************************************************************************/
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/* */
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/* Values : PNP CONTROL_REGISTER_1 */
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/* */
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/* These are the bit definitions for control register 1 on Smart 16 cards. */
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/* */
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/* NB. The bit definitions are mostly the same as MC CONTROL_REGISTER_1. */
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/* */
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#define PNP_CTRL1_NSRESET ((BYTE) 0x80) /* SIF Reset signal */
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#define PNP_CTRL1_CHRDY_ACTIVE ((BYTE) 0x20) /* Active channel ready. */
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/****************************************************************************/
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/* */
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/* This defines the bits used to set the RING SPEED for PNP cards. */
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/* */
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/* The bit is SET/CLEARED in SIFACL via adapter->nselout_bits just before */
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/* taking the card out of the RESET state. */
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/* */
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/* NSELOUT1 is use to control the ring speed */
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/* NSELOUT0 should ALWAYS be left alone. */
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/* */
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#define PNP_RING_SPEED_4 1
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#define PNP_RING_SPEED_16 0
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/*
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*
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* Various definitions used to talk to EEPROM.
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*
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*/
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#define PNP_CON_REG_OFFSET 4
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#define PNP_EEDO 0x0002
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#define PNP_EEDEN 0x0004
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#define PNP_SSK 0x0001
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#define PNP_DELAY_CNT 16
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#define PNP_WAIT_CNT 1000
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#define PNP_WRITE_CMD 0x00a0
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#define PNP_READ_CMD 0x00a1
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/*
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* Useful locations in the EEPROM
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*/
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#define PNP_HWARE_FEATURES1 0xEB
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#define PNP_HWARE_FEATURES3 0xED
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#define PNP_HWARE_PNP_FLAGS 0xEE
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/*
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*
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* This defines the bits in HWARE_FEATURES1 which give the DRAM size.
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*
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*/
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#define PNP_DRAM_SIZE_MASK 0x3E
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/*
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*
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* This defines the bits in HWARE_FEATURES3 which give the chip type.
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*
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*/
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#define PNP_C30_MASK 0x40
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#define PNP_C30 PNP_C30_MASK
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/*
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* This defines the bits in HWARE_PNP_FLAGS.
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*/
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#define PNP_ACTIVE_FLOAT_CHRDY 0x02
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/* */
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/* */
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/************** End of FTK_PNP.H file ***************************************/
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/* */
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/* */
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