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137 lines
6.9 KiB
137 lines
6.9 KiB
/***********************************************************************/
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/***********************************************************************/
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/* */
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/* File Name: ADAPTER.H */
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/* */
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/* Program Name: NetFlex NDIS 3.0 Driver */
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/* */
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/* Companion Files: None */
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/* */
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/* Function: This module contains all the adapter specific data */
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/* structure definitions that are specific to the */
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/* CPQTOK board. */
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/* */
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/* (c) Compaq Computer Corporation, 1992,1993 */
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/* */
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/* This file is licensed by Compaq Computer Corporation to Microsoft */
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/* Corporation pursuant to the letter of August 20, 1992 from */
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/* Gary Stimac to Mark Baber. */
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/* */
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/* History: */
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/* */
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/* 02/24/92 Carol Fuss - Reworked from NDIS driver */
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/* 06/14/93 Cat Abueg - Modified for MAPLE */
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/* 08/09/93 Cat Abueg - Modified for BONSAI */
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/* */
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/***********************************************************************/
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/***********************************************************************/
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/*
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* COMPAQ Token Ring Configuration Register definitions -
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* These equates define the bit settings in the CPQTOK
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* adapter's configuration registers.
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*/
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#define CFG_INTS 0xe000 /* Interrupt Level 5, 9 10, 11, 15 */
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#define CFG_INTRIG 0x1000 /* Interrupt Level Trigger */
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#define CFG_MEDIA 0x0800 /* Type 3 Media (else type 1) */
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#define CFG_16MBS 0x0400 /* 16Mbs select (else 4Mbs) */
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#define CFG_RSVD1 0x0300 /* Reserved */
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#define CFG_RSVD2 0x00f8 /* Reserved */
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#define CFG_ZERO 0x0006 /* Always zero */
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#define CFG_ENABLE 0x0001 /* Adapter Enable */
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/*
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* The following configuration registers are read as long words during
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* init time - i.e. 0xc84 and 0xc85, and 0x01b and 0x01c
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*/
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//define CFG_REGISTER 0xc84 /* Configuration register */
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#define CFG_REGISTER 0x4 /* Configuration register */
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/* Actual value = 0xc85 */
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#define CFG_REGRODAN 0x01b /* Cfg reg for 2nd port of Rodan */
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/* Actual value = 0x01c */
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#define CFG_REG2_OFF 0x01c /* ext cfg reg for 2nd port of Rodan */
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/* Actual value = 0x01c */
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#define COMPAQ_ID 0x110e /* Product Register ID */
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#define CPQTOK_ID 0x0060 /* Cpqtok's board ID */
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#define DURANGO_ID 0x0260 /* Durango's board ID */
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#define NETFLEX_ID 0x0061 /* NETFLEX's board ID */
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#define MAPLE_ID 0x0161 /* Manitu's board ID */
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#define BONSAI_ID 0x0062 /* Bonsai board ID */
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#define RODAN_ID 0x0063 /* Rodan board ID */
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#define NETFLEX_REVMASK 0xf0ff /* Board ID revision mask - MAJ */
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#define NETFLEX_MINMASK 0xff00 /* Board ID revision mask - MIN */
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#define PAGE3_MASK 0xc0000000 /* PCI mask - for < TRIC 5 */
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#define CFG_DUALPT_ADP1 0x0800 /* Type of connection for adp 1 */
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#define CFG_DUALPT_ADP2 0x0400 /* Type of connection for adp 2 */
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#define CFG_FULL_DUPLEX 0x04 /* Mask For Full Duplex */
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#define CFG_FULL_DUPLEX_HEAD2 0x08 /* Mask For Full Duplex Bonsai H2 */
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#define DUALHEAD_CFG_PORT_OFFSET 0x20 /* base port range for dual head z020 - z02e */
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#define CFG_PORT_OFFSET 0xc80 /* adapter configuration ports */
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#define EXTCFG_PORT_OFFSET 0xc63 /* extra adapter configuration ports */
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#define NUM_BASE_PORTS 0x20 /* z0000 - z001f */
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#define NUM_CFG_PORTS 0x8 /* z0c80 - z0c87 */
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#define NUM_EXTCFG_PORTS 0x5 /* z0c63 - z0c67 */
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#define NUM_DUALHEAD_CFG_PORTS 0x30 /* z000 - z02F */
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#define COLL_DETECT_ENABLED 0x8 /* bit 7 = 1 if collision enabled */
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#define LOOP_BACK_ENABLE_OFF 0x2 /* added to 0zc63 = 0Zc65 */
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#define LOOP_BACK_STATUS_OFF 0x1 /* added to 0zc63 = 0Zc64 */
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#define LOOP_BACK_ENABLE_HEAD1_OFF 0x3 /* added to 0zc63 = 0Zc66 */
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#define LOOP_BACK_STATUS_HEAD1_OFF 0x3 /* added to 0zc63 = 0Zc66 */
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#define LOOP_BACK_ENABLE_HEAD2_OFF 0x4 /* added to 0zc63 = 0Zc67 */
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#define LOOP_BACK_STATUS_HEAD2_OFF 0x4 /* added to 0zc63 = 0Zc67 */
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#define SWAPL(x) (((ULONG)(x) << 24) | \
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(((ULONG)(x) >> 24) & 0x000000ff) | \
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(((ULONG)(x) << 8) & 0x00ff0000) | \
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(((ULONG)(x) >> 8) & 0x0000ff00))
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#define SWAPS(x) (((USHORT)(x) << 8) | (((USHORT)(x) >> 8) & 0x00ff))
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#define CTRL_ADDR(x) ((x) | 0x80000000)
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#define MAKE_ODD(x) (x |= 0x1000000)
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#define MAKE_EVEN(x) (x &= ~0x1000000)
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#define TOKENMTU 4096 /* Token-Ring maximum packet size */
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#define MIN_TPKT 14 /* Minimunm packet size */
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#define CMD_ASYNCH 0
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#define CMD_SYNCH 1
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#define HARD_RESET 0
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#define SOFT_RESET 1
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#define DBM_NOT_SET 0
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#define DBM_RECV_ONLY 1
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#define DBM_XMIT_ONLY 2
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#define DBM_RECV_XMIT 3
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#define NETFLEX_INIT_ERROR_CODE ((ULONG) 0x1111)
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#define NETFLEX_RESET_FAILURE_ERROR_CODE ((ULONG) 0x2222)
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#define NETFLEX_ADAPTERCHECK_ERROR_CODE ((ULONG) 0x3333)
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#define NETFLEX_RINGSTATUS_ERROR_CODE ((ULONG) 0x4444)
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//
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// Structure Name: Download Structure Definition
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//
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// Description: The Download Structure Definition defines the structure
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// of the code/data to download to the TMS380 chipset.
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//
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typedef struct dl_struct
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{
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USHORT dl_chap; /* Section hi address */
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USHORT dl_addr; /* Section lo address */
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USHORT dl_bytes; /* Section length in bytes */
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} DL_STRUCT, *PDL_STRUCT;
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