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303 lines
7.2 KiB
303 lines
7.2 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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init.h
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Abstract:
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This is the init header file for the Ungermann Bass Ethernet Controller.
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This file contains definitions and macros used in initializing various
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variables at driver entry (or init ) time.
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Author:
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Sanjeev Katariya (sanjeevk) 03-05-92
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Environment:
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Kernel Mode Operating Systems : NT and other lesser OS's(dos)
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Revision History:
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Brian Lieuallen BrianLie 12/15/93
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Made it a mini-port
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--*/
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#include "packon.h"
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//
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// ADAPTER TYPES
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//
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#define PCNIU 0
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#define COST_REDUCED_PCNIU 1
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#define NIUPC 2
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#define NIUPS 3
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#define GPCNIU 4 // Ungermann Bass NIUpc/EOTP
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#define PCNIUEX 5
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//
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// ADAPTER CLASSES
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//
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#define PHOENIX 0
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#define ATLANTA 1
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#define CHAMELEON 2
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//
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// BITS IN ADAPTER CONTROL PORT DATA
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//
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#define DO_PARITY_CHECK_BIT 4
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#define x12V_BIT 2
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#define LED_BIT 1
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//
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//
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//
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//#define INTERRUPT_CONTROL_BIT 0x2
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//
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// BITS IN ADAPTER FLAGS
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//
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#define TWO_PASS_DIAGNOSTICS 0x80
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#define USE_INTERFACE_PORT 0x40
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#define ASYNCHRONOUS_READY 0x20
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//
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// ADAPTER DESCRIPTIONS
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//
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#define PCNIU_DESCRIPTION "Ungermann-Bass Personal NIU"
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#define NIUPC_DESCRIPTION "Ungermann-Bass NIUpc"
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#define NIUPS_DESCRIPTION "Ungermann-Bass NIUps or NIUps/EOTP"
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#define GPCNIU_DESCRIPTION "Ungermann-Bass NIUpc/EOTP"
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#define PCNIUEX_DESCRIPTION "Ungermann-Bass Personal NIU/ex"
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// DEFAULT HARDWARE SETTINGS
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//
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// Default hardware settings for ANY Ungermann Bass card
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// supported by this driver
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//
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#define DEFAULT_IO_BASEADDRESS (UINT)0x368
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#define DEFAULT_ADAPTER_TYPE GPCNIU
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#define DEFAULT_INTERRUPT_NUMBER 5
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#define DEFAULT_MEMORY_WINDOW (UINT)0xD8000
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#define NIU_CONTROL_AREA_OFFSET (USHORT)0xFF00
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//
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// Default hardware settings for specific Ungermann Bass cards
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//
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//
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// GPCNIU CARD
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//
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//
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// Settings of I/O Base Address jumper on the NIUpc/EOTP card.
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// Choices are 0x300, 0x310, 0x330, 0x350, 0x250, 0x280, 0x2a0, and 0x2e0.
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//
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#define DEFAULT_GPCNIU_IO_BASEADDRESS (UINT)0x360
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//
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// Setting for the interrupt number the NIUpc/EOTP board is using.
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// Choices are 2, 3, 4, 5, 7 or 12.
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//
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#define DEFAULT_GPCNIU_INTERRUPT_NUMBER 3
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//
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// Shared memory setting for the NIUpc/EOTP adapter.
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// are 0xd8000,
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//
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#define DEFAULT_GPCNIU_MEMORY_WINDOW 0xD8000
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#define GPCNIU_MINIMUM_WINDOW_SIZE 0x4000
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#define GPCNIU_OPERATIONAL_CS 0x2000
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#define GPCNIU_PRIMARY_DS 0x3000
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#define GPCNIU_TX_BUFFER_SEGS 0x3000
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#define GPCNIU_HIGHEST_RAM_SEGS 0x7000
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#define GPCNIU_SCSP_SEGS 0x7000
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#define GPCNIU_POD_STATUS_ADDR 0xFF80
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#define GPCNIU_HOST_INTR_PORT 0x3000
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#define GPCNIU_82586_CA_PORT 0x0080
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#define GPCNIU_82586_RESET_PORT 0x0280
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#define GPCNIU_ADAPTER_CTRL_PORT 0x0200
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#define GPCNIU_IRQSEL_LEDPORT 0x0180
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#define GPCNIU_DEADMAN_TIMERPORT 0x1006
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#define GPCNIU_LEDOFF_12V_DOPARCHK x12V_BIT
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#define GPCNIU_LEDON_12V_DOPARCHK x12V_BIT+LED_BIT
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#define GPCNIU_ADAPTER_FLAGS TWO_PASS_DIAGNOSTICS+ASYNCHRONOUS_READY
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#define GPCNIU_ADAPTER_CODE 'G'
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#define NIUPS_ADAPTER_CODE 'Y'
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#define GPCNIU_CLI_OFFSET 0x0
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#define GPCNIU_MAP_OFFSET 0x0
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#define GPCNIU_INTR_STATUS_OFFSET 0x1
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#define GPCNIU_SETWINBASE_OFFSET 0x2
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#define GPCNIU_NEXT_RAM_PAGE ((UCHAR)(WINDOWSIZE >> 8*3))
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#define NIUPC_MINIMUM_WINDOW_SIZE 0x8000
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#define NIUPC_OPERATIONAL_CS 0x2000
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#define NIUPC_PRIMARY_DS 0x3000
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#define NIUPC_TX_BUFFER_SEGS 0x3000
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#define NIUPC_HIGHEST_RAM_SEGS 0x3000
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#define NIUPC_SCSP_SEGS 0x3000
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#define NIUPC_POD_STATUS_ADDR 0xFEF8
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#define NIUPC_HOST_INTR_PORT 0x0100
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#define NIUPC_82586_CA_PORT 0x0080
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#define NIUPC_82586_RESET_PORT 0x0280
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#define NIUPC_ADAPTER_CTRL_PORT 0x0200
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#define NIUPC_IRQSEL_LEDPORT 0x0000
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#define NIUPC_DEADMAN_TIMERPORT 0x0018
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#define NIUPC_LEDOFF_12V_DOPARCHK x12V_BIT+DO_PARITY_CHECK_BIT+LED_BIT
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#define NIUPC_LEDON_12V_DOPARCHK x12V_BIT+DO_PARITY_CHECK_BIT
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#define NIUPC_ADAPTER_FLAGS 0
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#define NIUPC_ADAPTER_CODE 'V'
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#define NIUPC_CLI_OFFSET 0x0
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#define NIUPC_MAP_OFFSET 0x0
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#define NIUPC_INTR_STATUS_OFFSET 0x0
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#define NIUPC_SETWINBASE_OFFSET 0x0
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// DEFAULT HARDWARE SETTINGS:END
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//
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// The NIU control area in the InitWindowPage.
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// Starts at offset:
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//
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// (MemMapped)SharedMemBase + NIU_CONTROL_AREA_OFFSET(0xFF00)
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//
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typedef struct _NIUDETAILS {
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UCHAR MappingTable[0x20];
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USHORT AdapterClass;
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USHORT MinimumWindowSize;
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USHORT OperationalCodeSegment;
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USHORT PrimaryDataSegment;
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USHORT TransmitBufferSegment;
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USHORT HighestRamSegment;
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USHORT SCPSegment;
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USHORT POD_Status_Address;
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USHORT HostInterruptPort;
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USHORT _82586_CA_Port;
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USHORT _82586_RESET_Port;
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USHORT AdapterControlPort;
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UCHAR LED_Off_12Volts_DoParityCheck;
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UCHAR LED_On_12Volts_DoParityCheck;
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USHORT IRQ_Select_And_LED_Port;
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USHORT DeadManTimerPort;
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UCHAR IO_PortOffset[4];
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UCHAR AdapterFlags;
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UCHAR AdapterCode;
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} NIUDETAILS, *PNIUDETAILS;
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typedef struct tagOtherRingBufferDesc {
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UCHAR ORB_WritePtr_Byte;
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UCHAR res1;
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UCHAR ORB_ReadPtr_Byte;
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UCHAR res2;
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UCHAR ORB_PtrLimit;
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UCHAR ORB_ElementSize;
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USHORT ORB_BufferBase;
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USHORT ORB_Windowed_BufferBase;
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UCHAR ORB_ObjectMap;
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UCHAR ORB_pad[5];
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} ORB, *PORB;
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typedef struct tagRequest_RingBuffer_Entry {
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USHORT RequestCode;
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USHORT RequestID;
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USHORT RequestParam1;
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UCHAR RequestData[6];
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} RRBE, *PRRBE;
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typedef struct tagResult_RingBuffer_Entry {
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USHORT ResultID;
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USHORT ResultCode;
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} RESULTRBE, *PRESULTRBE;
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typedef struct tagTBD {
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USHORT TBD_EOF_and_Length;
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USHORT TBD_next_TBD;
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USHORT TBD_Buffer;
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UCHAR TBD_Buffer_MSB;
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UCHAR TBD_Buffer_Map;
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USHORT TBD_Frame_Length;
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UCHAR TBD_Unused;
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UCHAR TBD_Flags;
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USHORT TBD_next_TDB_offset;
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USHORT TBD_Buffer_offset;
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} TBD, *PTBD;
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typedef struct tagRBD {
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USHORT RBD_EOF_F_and_Length;
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USHORT RBD_next_RBD;
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USHORT RBD_Buffer;
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UCHAR RBD_Buffer_MSB;
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UCHAR RBD_Owner;
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USHORT RBD_EOL_and_Size;
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USHORT RBD_Buffer_Segment;
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USHORT RBD_Frame_Length;
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UCHAR RBD_Flags;
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UCHAR RBD_unused;
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} RBD, *PRBD;
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typedef struct tagMCB {
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UCHAR res;
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UCHAR MCB_Status;
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USHORT MCB_Command;
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USHORT next_CB;
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USHORT MCB_Count;
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} MCB, *PMCB;
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// SYSTEM mode Bits
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#define BROADBAND_MODE 0x8000
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#define INTERNAL_READY_SYNC 0x4000
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// System_State bits
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#define INITIALIZED 0x8000
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#include "packoff.h"
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