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786 lines
18 KiB
786 lines
18 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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axebsup.c
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Abstract:
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The module provides the EISA bus support for Alpha/Jensen systems.
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Author:
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Jeff Havens (jhavens) 19-Jun-1991
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Miche Baker-Harvey (miche) 13-May-1992
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Jeff McLeman (DEC) 1-Jun-1992
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Revision History:
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11-Mar-1993 Joe Mitchell (DEC)
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Added support for NMI interrupts: Added interrupt service routine
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HalHandleNMI. Added code to HalpCreateEisaStructures to initialize
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NMI interrupts.
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22-Jul-1992 Jeff McLeman (mcleman)
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Removed eisa xfer routines, since this is done in JXHWSUP
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02-Jul-92 Jeff McLeman (mcleman)
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Removed alphadma.h header file. This file was not needed since
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the DMA structure is described in the eisa header. Also add
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a note describing eisa references in this module.
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13-May-92 Stole file jxebsup.c and converted for Alpha/Jensen
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--*/
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// ** note **
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// This module has routines that manipulate eisa on alpha machines. On
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// the jensen machine, this is done in jxhwsup.c . These routines
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// would be used for an alpha machine that had a local bus and an
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// eisa bus.
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//
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#include "halp.h"
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#include "jnsndef.h"
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#include "jnsnint.h"
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#include "eisa.h"
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//
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// Define the context structure for use by the interrupt routine.
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//
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typedef BOOLEAN (*PSECONDARY_DISPATCH)(
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PVOID InterruptRoutine,
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PKTRAP_FRAME TrapFrame
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);
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//
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// Declare the interupt structure and spinlock for the intermediate EISA
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// interrupt dispachter.
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//
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KINTERRUPT HalpEisaInterrupt;
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/* [jrm 3/8/93] Add support for NMI interrupts */
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//
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// The following is the interrupt object used for DMA controller interrupts.
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// DMA controller interrupts occur when a memory parity error occurs or a
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// programming error occurs to the DMA controller.
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//
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KINTERRUPT HalpEisaNmiInterrupt;
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UCHAR EisaNMIMsg[] = "NMI: Eisa IOCHKERR board x\n";
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//
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// The following function is called when an EISA NMI occurs.
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//
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BOOLEAN
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HalHandleNMI(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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);
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//
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// Define save area for ESIA adapter objects.
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//
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PADAPTER_OBJECT HalpEisaAdapter[8];
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//
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// Define save area for EISA interrupt mask registers and level\edge control
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// registers.
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//
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UCHAR HalpEisaInterrupt1Mask;
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UCHAR HalpEisaInterrupt2Mask;
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UCHAR HalpEisaInterrupt1Level;
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UCHAR HalpEisaInterrupt2Level;
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BOOLEAN
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HalpCreateEisaStructures (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the structures necessary for EISA operations
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and connects the intermediate interrupt dispatcher. It also initializes the
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EISA interrupt controller.
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Arguments:
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None.
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Return Value:
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If the second level interrupt dispatcher is connected, then a value of
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TRUE is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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UCHAR DataByte;
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KIRQL oldIrql;
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//
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// Initialize the EISA NMI interrupt.
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//
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KeInitializeInterrupt( &HalpEisaNmiInterrupt,
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HalHandleNMI,
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NULL,
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NULL,
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EISA_NMI_VECTOR,
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EISA_NMI_LEVEL,
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EISA_NMI_LEVEL,
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LevelSensitive,
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FALSE,
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0,
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FALSE
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);
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//
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// Don't fail if the interrupt cannot be connected.
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//
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KeConnectInterrupt( &HalpEisaNmiInterrupt );
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//
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// Clear the Eisa NMI disable bit. This bit is the high order of the
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// NMI enable register.
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//
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DataByte = 0;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable,
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DataByte
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);
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//
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// Enable Software-Generated NMI interrupts by setting bit 1 of port 0x461.
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//
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DataByte = 0x02;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->ExtendedNmiResetControl,
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DataByte
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);
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//
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// Initialize the EISA interrupt dispatcher for Jazz I/O interrupts.
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//
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KeInitializeInterrupt( &HalpEisaInterrupt,
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HalpEisaDispatch,
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(PVOID) EISA_INTA_CYCLE_VIRTUAL_BASE,
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(PKSPIN_LOCK)NULL,
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PIC_VECTOR,
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EISA_DEVICE_LEVEL,
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EISA_DEVICE_LEVEL,
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LevelSensitive,
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TRUE,
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0,
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FALSE
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);
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if (!KeConnectInterrupt( &HalpEisaInterrupt )) {
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return(FALSE);
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}
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//
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// Raise the IRQL while the EISA interrupt controller is initalized.
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//
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KeRaiseIrql(EISA_DEVICE_LEVEL, &oldIrql);
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//
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// Initialize the EISA interrupt controller. There are two cascaded
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// interrupt controllers, each of which must initialized with 4 initialize
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// control words.
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//
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DataByte = 0;
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((PINITIALIZATION_COMMAND_1) &DataByte)->Icw4Needed = 1;
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((PINITIALIZATION_COMMAND_1) &DataByte)->InitializationFlag = 1;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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DataByte
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
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DataByte
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);
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//
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// The second intitialization control word sets the iterrupt vector to
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// 0-15.
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//
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DataByte = 0;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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DataByte = 0x08;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// The thrid initialization control word set the controls for slave mode.
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// The master ICW3 uses bit position and the slave ICW3 uses a numberic.
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//
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DataByte = 1 << SLAVE_IRQL_LEVEL;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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DataByte = SLAVE_IRQL_LEVEL;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// The fourth initialization control word is used to specify normal
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// end-of-interrupt mode and not special-fully-nested mode.
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//
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DataByte = 0;
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((PINITIALIZATION_COMMAND_4) &DataByte)->I80x86Mode = 1;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// Disable all of the interrupts except the slave.
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//
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HalpEisaInterrupt1Mask = ~(1 << SLAVE_IRQL_LEVEL);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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HalpEisaInterrupt1Mask
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);
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HalpEisaInterrupt2Mask = 0xFF;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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HalpEisaInterrupt2Mask
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);
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//
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// Initialize the edge/level register masks to 0 which is the default
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// edge sensitive value.
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//
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HalpEisaInterrupt1Level = 0;
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HalpEisaInterrupt2Level = 0;
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//
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// Restore IRQL level.
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//
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KeLowerIrql(oldIrql);
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//
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// Initialize the DMA mode registers to a default value.
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// Disable all of the DMA channels except channel 4 which is the
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// cascade of channels 0-3.
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask,
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0x0F
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask,
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0x0E
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);
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return(TRUE);
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}
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BOOLEAN
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HalpEisaDispatch(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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)
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/*++
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Routine Description:
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This routine is entered as the result of an interrupt being generated
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via the vector that is connected to an interrupt object that describes
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the EISA device interrupts. Its function is to call the second
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level interrupt dispatch routine and acknowledge the interrupt at the EISA
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controller.
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This service routine should be connected as follows:
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KeInitializeInterrupt(&Interrupt, HalpEisaDispatch,
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EISA_VIRTUAL_BASE,
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(PKSPIN_LOCK)NULL, EISA_LEVEL, EISA_LEVEL, EISA_LEVEL,
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LevelSensitive, TRUE, 0, FALSE);
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KeConnectInterrupt(&Interrupt);
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Arguments:
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Interrupt - Supplies a pointer to the interrupt object.
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ServiceContext - Supplies a pointer to the EISA interrupt acknowledge
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register.
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Return Value:
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Returns the value returned from the second level routine.
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--*/
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{
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UCHAR interruptVector;
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PKPRCB Prcb;
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BOOLEAN returnValue;
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USHORT PCRInOffset;
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UCHAR Int1Isr;
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UCHAR Int2Isr;
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PULONG DispatchCode;
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PKINTERRUPT InterruptObject;
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//
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// Read the interrupt vector.
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//
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interruptVector = READ_PORT_UCHAR(ServiceContext);
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//
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// schedule the read
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//
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HalpMb();
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KeStallExecutionProcessor(1);
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interruptVector = READ_PORT_UCHAR(ServiceContext);
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if ((interruptVector & 0x07) == 0x07) {
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//
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// Check for a passive release by looking at the inservice register.
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// If there is a real IRQL7 interrupt, just go along normally. If there
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// is not, then it is a passive release. So just dismiss it.
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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0x0B
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);
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Int1Isr = READ_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0);
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//
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// do second controller
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
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0x0B
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);
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Int2Isr = READ_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0);
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if (!(Int2Isr & 0x80) && !(Int1Isr & 0x80)) {
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//
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// Clear the master controller to clear situation
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//
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if (!(Int2Isr & 0x80)) {
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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NONSPECIFIC_END_OF_INTERRUPT
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);
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}
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return(TRUE);
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}
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}
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//
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// Dispatch to the secondary interrupt service routine.
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//
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PCRInOffset = interruptVector + EISA_VECTORS;
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DispatchCode = PCR->InterruptRoutine[PCRInOffset];
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InterruptObject = CONTAINING_RECORD(DispatchCode,
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KINTERRUPT,
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DispatchCode);
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returnValue = ((PSECONDARY_DISPATCH) InterruptObject->DispatchAddress)(
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InterruptObject,
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NULL);
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//
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// Dismiss the interrupt in the EISA interrupt controllers.
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//
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//
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// If this is a cascaded interrupt then the interrupt must be dismissed in
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// both controlles.
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//
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if (interruptVector & 0x08) {
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
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NONSPECIFIC_END_OF_INTERRUPT
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);
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}
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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NONSPECIFIC_END_OF_INTERRUPT
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);
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return(returnValue);
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}
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|
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VOID
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HalpDisableEisaInterrupt(
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IN ULONG Vector
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)
|
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|
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/*++
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Routine Description:
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This function Disables the EISA bus specified EISA bus interrupt.
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Arguments:
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Vector - Supplies the vector of the ESIA interrupt that is Disabled.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the EISA interrupt vector.
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//
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Vector -= EISA_VECTORS;
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|
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//
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// Determine if this vector is for interrupt controller 1 or 2.
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//
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if (Vector & 0x08) {
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//
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// The interrupt is in controller 2.
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//
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Vector &= 0x7;
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HalpEisaInterrupt2Mask |= (UCHAR) 1 << Vector;
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WRITE_PORT_UCHAR(
|
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
|
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HalpEisaInterrupt2Mask
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);
|
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|
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} else {
|
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|
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//
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// The interrupt is in controller 1.
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//
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Vector &= 0x7;
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|
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//
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// never disable IRQL2, it is the slave interrupt
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//
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if (Vector != SLAVE_IRQL_LEVEL) {
|
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HalpEisaInterrupt1Mask |= (ULONG) 1 << Vector;
|
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WRITE_PORT_UCHAR(
|
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
|
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HalpEisaInterrupt1Mask
|
|
);
|
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}
|
|
|
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}
|
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|
|
}
|
|
|
|
VOID
|
|
HalpEnableEisaInterrupt(
|
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IN ULONG Vector,
|
|
IN KINTERRUPT_MODE InterruptMode
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function enables the EISA bus specified EISA bus interrupt and sets
|
|
the level/edge register to the requested value.
|
|
|
|
Arguments:
|
|
|
|
Vector - Supplies the vector of the ESIA interrupt that is enabled.
|
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|
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
|
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Latched.
|
|
|
|
Return Value:
|
|
|
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None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
//
|
|
// Calculate the EISA interrupt vector.
|
|
//
|
|
|
|
Vector -= EISA_VECTORS;
|
|
|
|
//
|
|
// Determine if this vector is for interrupt controller 1 or 2.
|
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//
|
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|
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if (Vector & 0x08) {
|
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|
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//
|
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// The interrupt is in controller 2.
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//
|
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|
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Vector &= 0x7;
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|
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HalpEisaInterrupt2Mask &= (UCHAR) ~(1 << Vector);
|
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WRITE_PORT_UCHAR(
|
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
|
|
HalpEisaInterrupt2Mask
|
|
);
|
|
|
|
//
|
|
// Set the level/edge control register.
|
|
//
|
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|
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if (InterruptMode == LevelSensitive) {
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|
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HalpEisaInterrupt2Level |= (UCHAR) (1 << Vector);
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|
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} else {
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|
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HalpEisaInterrupt2Level &= (UCHAR) ~(1 << Vector);
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|
|
}
|
|
|
|
WRITE_PORT_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2EdgeLevel,
|
|
HalpEisaInterrupt2Level
|
|
);
|
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|
|
} else {
|
|
|
|
//
|
|
// The interrupt is in controller 1.
|
|
//
|
|
|
|
Vector &= 0x7;
|
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|
|
HalpEisaInterrupt1Mask &= (UCHAR) ~(1 << Vector);
|
|
WRITE_PORT_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
|
|
HalpEisaInterrupt1Mask
|
|
);
|
|
|
|
//
|
|
// Set the level/edge control register.
|
|
//
|
|
|
|
if (InterruptMode == LevelSensitive) {
|
|
|
|
HalpEisaInterrupt1Level |= (UCHAR) (1 << Vector);
|
|
|
|
} else {
|
|
|
|
HalpEisaInterrupt1Level &= (UCHAR) ~(1 << Vector);
|
|
|
|
}
|
|
|
|
WRITE_PORT_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1EdgeLevel,
|
|
HalpEisaInterrupt1Level
|
|
);
|
|
}
|
|
|
|
}
|
|
|
|
BOOLEAN
|
|
HalHandleNMI(
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is called when an EISA NMI occurs. It print the appropriate
|
|
status information and bugchecks.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the interrupt object
|
|
|
|
ServiceContext - Bug number to call bugcheck with.
|
|
|
|
Return Value:
|
|
|
|
Returns TRUE.
|
|
|
|
--*/
|
|
{
|
|
UCHAR StatusByte;
|
|
UCHAR EisaPort;
|
|
ULONG port;
|
|
ULONG AddressSpace = 1; // 1 = I/O address space
|
|
BOOLEAN Status;
|
|
PHYSICAL_ADDRESS BusAddress;
|
|
PHYSICAL_ADDRESS TranslatedAddress;
|
|
|
|
StatusByte =
|
|
READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus);
|
|
|
|
if (StatusByte & 0x80) {
|
|
HalDisplayString ("NMI: Parity Check / Parity Error\n");
|
|
}
|
|
|
|
if (StatusByte & 0x40) {
|
|
HalDisplayString ("NMI: Channel Check / IOCHK\n");
|
|
}
|
|
|
|
//
|
|
// This is an Eisa machine, check for extnded nmi information...
|
|
//
|
|
|
|
StatusByte = READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->ExtendedNmiResetControl);
|
|
|
|
if (StatusByte & 0x80) {
|
|
HalDisplayString ("NMI: Fail-safe timer\n");
|
|
}
|
|
|
|
if (StatusByte & 0x40) {
|
|
HalDisplayString ("NMI: Bus Timeout\n");
|
|
}
|
|
|
|
if (StatusByte & 0x20) {
|
|
HalDisplayString ("NMI: Software NMI generated\n");
|
|
}
|
|
|
|
//
|
|
// Look for any Eisa expansion board. See if it asserted NMI.
|
|
//
|
|
|
|
BusAddress.HighPart = 0;
|
|
|
|
for (EisaPort = 0; EisaPort <= 0xf; EisaPort++)
|
|
{
|
|
BusAddress.LowPart = (EisaPort << 12) + 0xC80;
|
|
|
|
Status = HalTranslateBusAddress(Eisa, // InterfaceType
|
|
0, // BusNumber (0 for Jensen)
|
|
BusAddress,
|
|
&AddressSpace, // 1=I/O address space
|
|
&TranslatedAddress); // QVA
|
|
if (Status == FALSE)
|
|
{
|
|
UCHAR pbuf[80];
|
|
sprintf(pbuf,
|
|
"Unable to translate bus address %x for EISA slot %d\n",
|
|
BusAddress.LowPart, EisaPort);
|
|
HalDisplayString(pbuf);
|
|
KeBugCheck(NMI_HARDWARE_FAILURE);
|
|
}
|
|
|
|
port = TranslatedAddress.LowPart;
|
|
|
|
WRITE_PORT_UCHAR ((PUCHAR) port, 0xff);
|
|
StatusByte = READ_PORT_UCHAR ((PUCHAR) port);
|
|
|
|
if ((StatusByte & 0x80) == 0) {
|
|
//
|
|
// Found valid Eisa board, Check to see if it's
|
|
// if IOCHKERR is asserted.
|
|
//
|
|
|
|
StatusByte = READ_PORT_UCHAR ((PUCHAR) port+4);
|
|
if (StatusByte & 0x2) {
|
|
EisaNMIMsg[25] = (EisaPort > 9 ? 'A'-10 : '0') + EisaPort;
|
|
HalDisplayString (EisaNMIMsg);
|
|
}
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
// Reset NMI interrupts (for debugging purposes only).
|
|
WRITE_PORT_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->ExtendedNmiResetControl, 0x00);
|
|
WRITE_PORT_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->ExtendedNmiResetControl, 0x02);
|
|
#endif
|
|
|
|
KeBugCheck(NMI_HARDWARE_FAILURE);
|
|
return(TRUE);
|
|
}
|