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299 lines
5.7 KiB
299 lines
5.7 KiB
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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contains copyrighted material. Use of this file is restricted
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by the provisions of a Motorola Software License Agreement.
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Copyright (c) 1995-96 International Business Machines Corporation
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Module Name:
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pxmemctl.c
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Abstract:
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The module initializes any planar registers.
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This module also implements machince check parity error handling.
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Author:
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Jim Wooldridge ([email protected])
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "pcip.h"
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extern PVOID HalpPciConfigBase;
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#define PCI_INTERRUPT_ROUTING_OTHER 15 //IBMCPK: should we really have seperate scsi int??
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#define PCI_INTERRUPT_ROUTING_SCSI PCI_INTERRUPT_ROUTING_OTHER
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGE,HalpGetPCIIrq)
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#endif
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ULONG HalpPciMaxSlots = PCI_MAX_DEVICES;
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ULONG
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HalpTranslatePciSlotNumber (
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ULONG BusNumber,
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ULONG SlotNumber
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)
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/*++
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Routine Description:
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This routine translate a PCI slot number to a PCI device number.
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This is a sandalfoot memory map implementation.
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Arguments:
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None.
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Return Value:
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Returns length of data written.
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--*/
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{
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//
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// Sandalfoot only has 1 PCI bus so bus number is unused
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//
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PCI_TYPE1_CFG_BITS PciConfig;
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PCI_SLOT_NUMBER PciSlotNumber;
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PciSlotNumber.u.AsULONG = SlotNumber;
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PciConfig.u.AsULONG = 0;
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PciConfig.u.bits.DeviceNumber = PciSlotNumber.u.bits.DeviceNumber;
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PciConfig.u.bits.FunctionNumber = PciSlotNumber.u.bits.FunctionNumber;
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PciConfig.u.bits.BusNumber = BusNumber;
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PciConfig.u.bits.Enable = TRUE;
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return (PciConfig.u.AsULONG);
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}
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ULONG
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HalpPhase0SetPciDataByOffset (
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ULONG BusNumber,
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ULONG SlotNumber,
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PUCHAR Buffer,
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ULONG Offset,
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ULONG Length
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)
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/*++
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Routine Description:
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This routine writes to PCI configuration space prior to bus handler installation.
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Arguments:
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None.
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Return Value:
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Returns length of data written.
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--*/
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{
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ULONG to;
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PUCHAR from;
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ULONG tmpLength;
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ULONG i;
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if (SlotNumber < HalpPciMaxSlots) {
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to = (ULONG) HalpPciConfigBase + (SlotNumber << 11);
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to += Offset;
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from = Buffer;
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tmpLength = Length;
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while (tmpLength > 0) {
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WRITE_PORT_ULONG ((PUCHAR)HalpIoControlBase + 0xCF8, to );
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i = to % sizeof(ULONG);
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WRITE_PORT_UCHAR ((PUCHAR)HalpIoControlBase + 0xCFC + i,*from);
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to++;
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from++;
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tmpLength--;
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}
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return(Length);
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}
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else {
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return (0);
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}
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}
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ULONG
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HalpPhase0GetPciDataByOffset (
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ULONG BusNumber,
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ULONG SlotNumber,
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PUCHAR Buffer,
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ULONG Offset,
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ULONG Length
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)
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/*++
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Routine Description:
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This routine reads PCI config space prior to bus handlder installation.
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Arguments:
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None.
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Return Value:
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Amount of data read.
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--*/
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{
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PUCHAR to;
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ULONG from;
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ULONG tmpLength;
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ULONG i;
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if (SlotNumber < HalpPciMaxSlots) {
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from = (ULONG) HalpPciConfigBase + (SlotNumber << 11);
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from += Offset;
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to = Buffer;
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tmpLength = Length;
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while (tmpLength > 0) {
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WRITE_PORT_ULONG ((PUCHAR)HalpIoControlBase + 0xCF8, from);
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i = from % sizeof(ULONG);
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*((PUCHAR) to) = READ_PORT_UCHAR ((PUCHAR)HalpIoControlBase + 0xCFC + i);
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to++;
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from++;
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tmpLength--;
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}
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return(Length);
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}
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else {
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return (0);
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}
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}
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NTSTATUS
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HalpGetPCIIrq (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER PciSlot,
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OUT PSUPPORTED_RANGE *Interrupt
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)
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{
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ULONG buffer[PCI_COMMON_HDR_LENGTH/sizeof(ULONG)];
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PPCI_COMMON_CONFIG PciData;
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#define PCI_VENDOR_NCR 0x1000
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PciData = (PPCI_COMMON_CONFIG) buffer;
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HalGetBusData (
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PCIConfiguration,
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BusHandler->BusNumber,
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PciSlot.u.AsULONG,
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PciData,
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PCI_COMMON_HDR_LENGTH
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);
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if (PciData->VendorID == PCI_INVALID_VENDORID ||
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PCI_CONFIG_TYPE (PciData) != 0) {
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return STATUS_UNSUCCESSFUL;
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}
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*Interrupt = ExAllocatePool (PagedPool, sizeof (SUPPORTED_RANGE));
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if (!*Interrupt) {
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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RtlZeroMemory (*Interrupt, sizeof (SUPPORTED_RANGE));
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if (PciSlot.u.bits.DeviceNumber == 2) {
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(*Interrupt)->Base = PCI_INTERRUPT_ROUTING_SCSI;
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(*Interrupt)->Limit = PCI_INTERRUPT_ROUTING_SCSI;
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} else {
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(*Interrupt)->Base = PCI_INTERRUPT_ROUTING_OTHER;
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(*Interrupt)->Limit = PCI_INTERRUPT_ROUTING_OTHER;
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}
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#if defined(SOFT_HDD_LAMP)
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if ( (PciData->BaseClass == 1) ||
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( (PciData->VendorID == PCI_VENDOR_NCR) && (PciData->DeviceID == 1) ) ) {
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//
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// This device is a Mass Storage Controller, set flag to
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// turn on the HDD Lamp when interrupts come in on this
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// vector.
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//
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// N.B. We recognize NCR 810 controllers as they were implemented
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// before class codes.
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//
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extern ULONG HalpMassStorageControllerVectors;
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HalpMassStorageControllerVectors |= 1 << (*Interrupt)->Base;
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}
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#endif
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return STATUS_SUCCESS;
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}
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VOID
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HalpMapPlugInPciBridges(
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UCHAR NoBuses
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)
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/*++
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Routine Description:
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Looks for any unexpected (plug-in) PCI-PCI bridges so
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that interrupts can be mapped from these buses back
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into the interrupt controller.
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Arguments:
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NoBuses -- This is the number of buses that HalpGetPciBridgeConfig found
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Return Value:
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none
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--*/
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{
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// Carolina supports some plug-in PCI busses, but this
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// HAL doesn't need to build the map because all Carolina PCI
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// interrupts are routed to the same IRQ. Hence the
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// map reduces to nothing.
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return;
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}
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