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396 lines
8.1 KiB
396 lines
8.1 KiB
/*++
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Copyright (c) 1991-1993 Microsoft Corporation
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Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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contains copyrighted material. Use of this file is restricted
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by the provisions of a Motorola Software License Agreement.
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Module Name:
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pxinithl.c
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Abstract:
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This module implements the initialization of the system dependent
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functions that define the Hardware Architecture Layer (HAL) for a
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Power PC system.
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Author:
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David N. Cutler (davec) 25-Apr-1991
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Environment:
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Kernel mode only.
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Revision History:
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Jim Wooldridge ([email protected]) Initial Power PC port
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Removed call to HalpMapFixedTbEntries, the PPC port
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maps all memory via calls to MmMapIoSpace().
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Removed call to HalpInitializeInterrupts - 8259 initialized in phase 1
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Removed Cache error handler - 601 has no cache error interrupt
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Removed call to HalpCreateDmaSturctures - it supports internal DMA
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--*/
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#include "halp.h"
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#include "pxmemctl.h"
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#include "pxsystyp.h"
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extern ADDRESS_USAGE HalpDefaultIoSpace;
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extern ULONG HalpPciMaxSlots;
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extern ULONG HalpPciConfigSize;
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ULONG
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HalpSizeL2Cache(
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VOID
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);
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VOID
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HalpSynchronizeExecution(
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VOID
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);
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VOID
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HalpCopyROMs(
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VOID
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);
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VOID HalpPatch_KeFlushWriteBuffer(VOID);
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//
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// Put all code for HAL initialization in the INIT section. It will be
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// deallocated by memory management when phase 1 initialization is
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// completed.
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//
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#if defined(ALLOC_PRAGMA)
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#pragma alloc_text(INIT, HalInitSystem)
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#pragma alloc_text(INIT, HalInitializeProcessor)
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#endif
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PVOID HalpIoControlBase = (PVOID) 0;
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ULONG L2_Cache_Size;
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VOID
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HalpInitBusHandlers (
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VOID
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);
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VOID
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HalpRegisterInternalBusHandlers (
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VOID
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);
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VOID
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HalpEnableEagleSettings(
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VOID
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);
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VOID
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HalpCheckHardwareRevisionLevels(
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VOID
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);
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VOID
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HalpDumpHardwareState(
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VOID
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);
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VOID
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HalpEnableL2Cache(
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VOID
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);
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//
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// Define global spin locks used to synchronize various HAL operations.
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//
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KSPIN_LOCK HalpBeepLock;
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KSPIN_LOCK HalpDisplayAdapterLock;
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KSPIN_LOCK HalpSystemInterruptLock;
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BOOLEAN
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HalInitSystem (
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IN ULONG Phase,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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This function initializes the Hardware Architecture Layer (HAL) for a
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Power PC system.
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Arguments:
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Phase - Supplies the initialization phase (zero or one).
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LoaderBlock - Supplies a pointer to a loader parameter block.
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Return Value:
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A value of TRUE is returned is the initialization was successfully
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complete. Otherwise a value of FALSE is returend.
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--*/
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{
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extern KSPIN_LOCK NVRAM_Spinlock;
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PKPRCB Prcb;
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//
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// Initialize the HAL components based on the phase of initialization
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// and the processor number.
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//
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Prcb = PCR->Prcb;
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if ((Phase == 0) || (Prcb->Number != 0)) {
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if (Prcb->Number == 0)
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HalpSetSystemType( LoaderBlock );
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//
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// Phase 0 initialization.
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//
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// N.B. Phase 0 initialization is executed on all processors.
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//
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//
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// Get access to I/O space, check if I/O space has already been
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// mapped by debbuger initialization.
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//
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if (HalpIoControlBase == NULL) {
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HalpIoControlBase = (PVOID)KePhase0MapIo(IO_CONTROL_PHYSICAL_BASE, 0x20000);
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if ( !HalpIoControlBase ) {
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return FALSE;
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}
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}
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//
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// Initialize the display adapter. Must be done early
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// so KeBugCheck() will be able to display
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//
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if (!HalpInitializeDisplay(LoaderBlock))
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return FALSE;
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// Verify that the processor block major version number conform
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// to the system that is being loaded.
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//
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if (Prcb->MajorVersion != PRCB_MAJOR_VERSION) {
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KeBugCheck(MISMATCHED_HAL);
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}
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//
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// If processor 0 is being initialized, then initialize various
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// variables, spin locks, and the display adapter.
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//
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if (Prcb->Number == 0) {
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//
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// Initialize Spinlock for NVRAM
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//
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KeInitializeSpinLock( &NVRAM_Spinlock );
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//
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// Set the interval clock increment value.
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//
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HalpCurrentTimeIncrement = MAXIMUM_INCREMENT;
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HalpNewTimeIncrement = MAXIMUM_INCREMENT;
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KeSetTimeIncrement(MAXIMUM_INCREMENT, MINIMUM_INCREMENT);
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//
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// Initialize all spin locks.
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//
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#if defined(_MP_PPC_)
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KeInitializeSpinLock(&HalpBeepLock);
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KeInitializeSpinLock(&HalpDisplayAdapterLock);
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KeInitializeSpinLock(&HalpSystemInterruptLock);
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#endif
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HalpRegisterAddressUsage (&HalpDefaultIoSpace);
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//
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// Calibrate execution stall
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//
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HalpCalibrateStall();
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//
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// Patch KeFlushWriteBuffer to the optimum code sequence
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//
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HalpPatch_KeFlushWriteBuffer();
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//
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// Size the L2 cache
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//
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L2_Cache_Size = HalpSizeL2Cache();
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PCR->SecondLevelIcacheSize = L2_Cache_Size << 10;
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PCR->SecondLevelDcacheSize = L2_Cache_Size << 10;
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//
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// Compute size of PCI Configuration Space mapping
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//
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HalpPciConfigSize = PAGE_SIZE * ((1 << (HalpPciMaxSlots-2)) + 1);
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//
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// Fill in handlers for APIs which this HAL supports
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//
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HalQuerySystemInformation = HaliQuerySystemInformation;
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HalSetSystemInformation = HaliSetSystemInformation;
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HalRegisterBusHandler = HaliRegisterBusHandler;
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HalHandlerForBus = HaliHandlerForBus;
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HalHandlerForConfigSpace = HaliHandlerForConfigSpace;
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}
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//
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// InitializeInterrupts
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//
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if (!HalpInitializeInterrupts())
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return FALSE;
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//
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// return success
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//
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return TRUE;
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} else {
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if (Phase != 1)
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return(FALSE);
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//
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// Phase 1 initialization.
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//
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// N.B. Phase 1 initialization is only executed on processor 0.
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//
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HalpRegisterInternalBusHandlers ();
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if (!HalpAllocateMapBuffer()) {
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return FALSE;
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}
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//
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// Map I/O space and create ISA data structures.
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//
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if (!HalpMapIoSpace()) {
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return FALSE;
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}
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if (!HalpCreateSioStructures()) {
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return FALSE;
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}
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HalpCheckHardwareRevisionLevels();
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HalpEnableL2Cache();
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HalpEnableEagleSettings();
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HalpDumpHardwareState();
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HalpCopyROMs();
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return TRUE;
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}
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}
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VOID
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HalInitializeProcessor (
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IN ULONG Number
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)
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/*++
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Routine Description:
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This function is called early in the initialization of the kernel
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to perform platform dependent initialization for each processor
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before the HAL Is fully functional.
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N.B. When this routine is called, the PCR is present but is not
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fully initialized. In order to access the PCR from this
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routine, use the PCRsprg1 macro, not the PCR macro.
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Arguments:
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Number - Supplies the number of the processor to initialize.
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Return Value:
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None.
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--*/
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{
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ULONG IcacheSize, DcacheSize;
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ULONG CacheBlockAlignment;
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switch (HalpGetProcessorVersion() >> 16) {
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case 1: // 601
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IcacheSize = 32*1024;
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DcacheSize = 32*1024;
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CacheBlockAlignment = 32 - 1;
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break;
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case 3: // 603
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IcacheSize = 8*1024;
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DcacheSize = 8*1024;
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CacheBlockAlignment = 32 - 1;
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break;
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case 6: // 603e
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case 7: // 603ev
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case 4: // 604
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IcacheSize = 16*1024;
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DcacheSize = 16*1024;
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CacheBlockAlignment = 32 - 1;
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break;
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case 9: // 604+
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IcacheSize = 32*1024;
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DcacheSize = 32*1024;
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CacheBlockAlignment = 32 - 1;
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break;
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default:
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KeBugCheck(HAL_INITIALIZATION_FAILED);
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return;
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}
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PCRsprg1->FirstLevelIcacheSize = IcacheSize;
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PCRsprg1->FirstLevelDcacheSize = DcacheSize;
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PCRsprg1->DcacheAlignment = CacheBlockAlignment;
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PCRsprg1->IcacheAlignment = CacheBlockAlignment;
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return;
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}
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