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880 lines
18 KiB
880 lines
18 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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ebinitnt.c
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Abstract:
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This module implements the platform-specific initialization for
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an EB64+ system.
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Author:
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Joe Notarangelo 25-Oct-1993
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Environment:
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Kernel mode only.
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Revision History:
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Dick Bissen [DEC] 30-Jun-1994
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Added code to support new PCI memory configuration.
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Dick Bissen [DEC] 12-May-1994
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Added code to support both passes of the EB64Plus modules.
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--*/
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#include "halp.h"
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#include "pcrtc.h"
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#include "eb64pdef.h"
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#include "halpcsl.h"
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#include "eisa.h"
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#include "pci.h"
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#include "pcip.h"
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#include "iousage.h"
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#include "flash8k.h"
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#include "fwcallbk.h"
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#include <ntverp.h> // to get the product build number.
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//
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// Define extern global buffer for the Uncorrectable Error Frame.
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// declared in halalpha\inithal.c
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//
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extern PERROR_FRAME PUncorrectableError;
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//
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// Define global data for builtin device interrupt enables.
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//
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USHORT HalpBuiltinInterruptEnable;
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//
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//
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//
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BOOLEAN SystemIsAlphaPC64;
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PVOID INTERRUPT_MASK0_QVA;
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PVOID INTERRUPT_MASK1_QVA;
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PVOID INTERRUPT_MASK2_QVA;
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ULONG SIO_INTERRUPT_MASK;
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// irql mask and tables
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//
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// irql 0 - passive
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// irql 1 - sfw apc level
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// irql 2 - sfw dispatch level
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// irql 3 - device low
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// irql 4 - device high
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// irql 5 - clock
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// irql 6 - real time, ipi, performance counters
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// irql 7 - error, mchk, nmi, halt
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//
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//
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// IDT mappings:
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// For the built-ins, GetInterruptVector will need more info,
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// or it will have to be built-in to the routines, since
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// these don't match IRQL levels in any meaningful way.
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//
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// 0 passive 8 perf cntr 1
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// 1 apc 9
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// 2 dispatch 10 PIC
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// 3 11
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// 4 12 errors
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// 5 clock 13
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// 6 perf cntr 0 14 halt
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// 7 nmi 15
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//
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// This is assuming the following prioritization:
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// nmi
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// halt
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// errors
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// performance counters
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// clock
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// pic
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//
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// The hardware interrupt pins are used as follows for EB64+
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//
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// IRQ_H[0] = PIC
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// IRQ_H[1] = Clock
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// IRQ_H[2] = NMI
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// IRQ_H[3] = unused
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// IRQ_H[4] = unused
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// IRQ_H[5] = unused
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//
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// For information purposes: here is what the IDT division looks like:
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//
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// 000-015 Built-ins (we only use 8 entries; NT wants 10)
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// 016-031 ISA
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// 048-063 EISA
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// 080-095 PCI
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// 112-127 Turbo Channel
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// 128-255 unused, as are all other holes
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//
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//
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// These globals make available the specifics of the Eb64 platform
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// we're running in.
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//
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BOOLEAN SioCStep;
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//
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// This is the PCI Sparse Memory space that cannot be used by anyone
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// and therefore the HAL says it is reserved for itself.
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//
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//
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// This is the PCI Memory space that cannot be used by anyone
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// and therefore the HAL says it is reserved for itself
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//
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ADDRESS_USAGE
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EB64pPCIMemorySpace = {
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NULL, CmResourceTypeMemory, PCIUsage,
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{
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__8MB, __32MB - __8MB, // Start=8MB; Length=24Mb (8 through 32)
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0,0
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}
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};
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//
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// Define the bus type, this value allows us to distinguish between
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// EISA and ISA systems.
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//
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ULONG HalpBusType = MACHINE_TYPE_ISA;
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//
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// Define global data used to communicate new clock rates to the clock
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// interrupt service routine.
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//
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ULONG HalpCurrentTimeIncrement;
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ULONG HalpNextRateSelect;
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ULONG HalpNextTimeIncrement;
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ULONG HalpNewTimeIncrement;
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VOID
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HalpInitializeHAERegisters(
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VOID
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);
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VOID
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HalpParseLoaderBlock(
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PLOADER_PARAMETER_BLOCK LoaderBlock
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);
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VOID
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HalpClearInterrupts(
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);
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BOOLEAN
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HalpInitializeInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This function initializes interrupts for an Alpha system.
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Arguments:
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None.
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Return Value:
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A value of TRUE is returned if the initialization is successfully
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completed. Otherwise a value of FALSE is returned.
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--*/
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{
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UCHAR DataByte;
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ULONG DataLong;
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ULONG Index;
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ULONG Irq;
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KIRQL Irql;
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UCHAR Priority;
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ULONG Vector;
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//
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// Initialize HAL processor parameters based on estimated CPU speed.
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// This must be done before HalpStallExecution is called. Compute integral
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// megahertz first to avoid rounding errors due to imprecise cycle clock
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// period values.
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//
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HalpInitializeProcessorParameters();
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//
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// Connect the Stall interrupt vector to the clock. When the
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// profile count is calculated, we then connect the normal
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// clock.
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PCR->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt;
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//
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// Clear all pending interrupts
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//
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HalpClearInterrupts();
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//
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// Start the periodic interrupt from the RTC
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//
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HalpProgramIntervalTimer(MAXIMUM_RATE_SELECT);
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//
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// Initialize the PCI/ISA interrupt controller.
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//
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HalpInitializePCIInterrupts();
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//
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// Initialize the 21064 interrupts.
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//
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HalpInitialize21064Interrupts();
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HalpEnable21064SoftwareInterrupt( Irql = APC_LEVEL );
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HalpEnable21064SoftwareInterrupt( Irql = DISPATCH_LEVEL );
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HalpEnable21064HardwareInterrupt(Irq = 0,
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Irql = DEVICE_LEVEL,
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Vector = PIC_VECTOR,
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Priority = 0 );
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HalpEnable21064HardwareInterrupt(Irq = 1,
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Irql = CLOCK_LEVEL,
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Vector = CLOCK_VECTOR,
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Priority = 0 );
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HalpEnable21064HardwareInterrupt(Irq = 2,
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Irql = HIGH_LEVEL,
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Vector = EISA_NMI_VECTOR,
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Priority = 0 );
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return TRUE;
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}
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VOID
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HalpClearInterrupts(
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)
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/*++
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Routine Description:
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This function no longer does anything.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalpSetTimeIncrement(
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VOID
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)
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/*++
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Routine Description:
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This routine is responsible for setting the time increment for an EV4
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based machine via a call into the kernel.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Set the time increment value.
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//
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HalpCurrentTimeIncrement = MAXIMUM_INCREMENT;
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HalpNextTimeIncrement = MAXIMUM_INCREMENT;
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HalpNextRateSelect = 0;
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KeSetTimeIncrement( MAXIMUM_INCREMENT, MINIMUM_INCREMENT );
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}
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//
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// Define global data used to calibrate and stall processor execution.
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//
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ULONG HalpProfileCountRate;
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VOID
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HalpInitializeClockInterrupts(
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VOID
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)
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/*++
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Routine Description:
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This function is called during phase 1 initialization to complete
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the initialization of clock interrupts. For EV4, this function
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connects the true clock interrupt handler and initializes the values
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required to handle profile interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Compute the profile interrupt rate.
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//
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HalpProfileCountRate = ((1000 * 1000 * 10) / KeQueryTimeIncrement());
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//
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// Set the time increment value and connect the real clock interrupt
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// routine.
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//
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PCR->InterruptRoutine[CLOCK2_LEVEL] = HalpClockInterrupt;
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return;
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}
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VOID
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HalpEstablishErrorHandler(
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VOID
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)
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/*++
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Routine Description:
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This routine performs the initialization necessary for the HAL to
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begin servicing machine checks.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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BOOLEAN ReportCorrectables;
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//
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// Connect the machine check handler via the PCR. The machine check
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// handler for EV4 is the default EV4 parity-mode handler.
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//
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PCR->MachineCheckError = HalMachineCheck;
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//
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// Initialize error handling for APECS.
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//
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HalpInitializeMachineChecks ( ReportCorrectables = FALSE );
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return;
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}
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VOID
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HalpInitializeMachineDependent(
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IN ULONG Phase,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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This function performs any EV4-specific initialization based on
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the current phase on initialization.
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Arguments:
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Phase - Supplies an indicator for phase of initialization, phase 0 or
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phase 1.
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LoaderBlock - supplies a pointer to the loader block.
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Return Value:
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None.
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--*/
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{
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ULONG PciBridgeHeaderOffset;
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ULONG SioRevision;
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if ( Phase == 0 ) {
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//
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// Phase 0 Initialization.
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//
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HalpFlashDriver = HalpInitializeFlashDriver((PCHAR)ALPHAPC64_ENVIRONMENT_QVA);
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if (HalpFlashDriver != NULL) {
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//
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// The flash device was found, so we must be running on an
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// AlphaPC64
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//
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SystemIsAlphaPC64 = TRUE;
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HalpCMOSRamBase = (PVOID)ALPHAPC64_ENVIRONMENT_QVA;
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INTERRUPT_MASK0_QVA = ALPHAPC64_INTERRUPT_MASK0_QVA;
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INTERRUPT_MASK1_QVA = ALPHAPC64_INTERRUPT_MASK1_QVA;
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INTERRUPT_MASK2_QVA = ALPHAPC64_INTERRUPT_MASK2_QVA;
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SIO_INTERRUPT_MASK = ALPHAPC64_SIO_INTERRUPT_MASK;
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} else {
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SystemIsAlphaPC64 = FALSE;
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INTERRUPT_MASK0_QVA = EB64P_INTERRUPT_MASK0_QVA;
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INTERRUPT_MASK1_QVA = EB64P_INTERRUPT_MASK1_QVA;
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INTERRUPT_MASK2_QVA = EB64P_INTERRUPT_MASK2_QVA;
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SIO_INTERRUPT_MASK = EB64P_SIO_INTERRUPT_MASK;
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}
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#ifdef HALDBG
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DbgPrint("HalpInitializeMachineDependent: SystemIsAlphaPC64 is %x\n",
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SystemIsAlphaPC64);
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DbgPrint("HalpInitializeMachineDependent: HalpCMOSRamBase is %x\n",
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HalpCMOSRamBase);
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DbgPrint("HalpInitializeMachineDependent: INTERRUPT_MASK0_QVA is %x\n",
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INTERRUPT_MASK0_QVA);
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DbgPrint("HalpInitializeMachineDependent: INTERRUPT_MASK1_QVA is %x\n",
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INTERRUPT_MASK1_QVA);
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DbgPrint("HalpInitializeMachineDependent: INTERRUPT_MASK2_QVA is %x\n",
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INTERRUPT_MASK2_QVA);
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DbgPrint("HalpInitializeMachineDependent: SIO_INTERRUPT_MASK is %x\n",
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SIO_INTERRUPT_MASK);
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#endif
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//
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// Parse the Loader Parameter block looking for PCI entry to determine
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// if PCI parity should be disabled
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//
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HalpParseLoaderBlock( LoaderBlock );
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//
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// Re-establish the error handler, to reflect the parity checking
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//
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HalpEstablishErrorHandler();
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PciBridgeHeaderOffset = PCI_ISA_BRIDGE_HEADER_OFFSET_P2;
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SioRevision = READ_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA |
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PciBridgeHeaderOffset |
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PCI_REVISION),
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PCI_CONFIG_CYCLE_TYPE_0);
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SioCStep = (SioRevision == 0x3 ? TRUE : FALSE);
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#ifdef HALDBG
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DbgPrint("HalpInitializeMachineDependent: SioCStep is %x\n",SioCStep);
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#endif
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HalpInitializeHAERegisters();
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} else {
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//
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// Phase 1 Initialization.
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//
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//
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// Initialize the existing bus handlers.
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//
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HalpRegisterInternalBusHandlers();
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//
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// Initialize the PCI bus.
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//
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HalpInitializePCIBus (LoaderBlock);
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//
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// Initialize the profiler.
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//
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HalpInitializeProfiler();
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}
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return;
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}
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VOID
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HalpStallInterrupt (
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VOID
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)
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/*++
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Routine Description:
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This function serves as the stall calibration interrupt service
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routine. It is executed in response to system clock interrupts
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during the initialization of the HAL layer.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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HalpAcknowledgeClockInterrupt();
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return;
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}
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ULONG
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HalSetTimeIncrement (
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IN ULONG DesiredIncrement
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)
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/*++
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Routine Description:
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This function is called to set the clock interrupt rate to the frequency
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required by the specified time increment value.
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Arguments:
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DesiredIncrement - Supplies desired number of 100ns units between clock
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interrupts.
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Return Value:
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The actual time increment in 100ns units.
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--*/
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{
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ULONG NewTimeIncrement;
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ULONG NextRateSelect;
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KIRQL OldIrql;
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//
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// Raise IRQL to the highest level, set the new clock interrupt
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// parameters, lower IRQl, and return the new time increment value.
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//
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KeRaiseIrql(HIGH_LEVEL, &OldIrql);
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if (DesiredIncrement < MINIMUM_INCREMENT) {
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DesiredIncrement = MINIMUM_INCREMENT;
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}
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if (DesiredIncrement > MAXIMUM_INCREMENT) {
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DesiredIncrement = MAXIMUM_INCREMENT;
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}
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//
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// Find the allowed increment that is less than or equal to
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// the desired increment.
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//
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if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS4) {
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NewTimeIncrement = RTC_PERIOD_IN_CLUNKS4;
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NextRateSelect = RTC_RATE_SELECT4;
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} else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS3) {
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NewTimeIncrement = RTC_PERIOD_IN_CLUNKS3;
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NextRateSelect = RTC_RATE_SELECT3;
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} else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS2) {
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NewTimeIncrement = RTC_PERIOD_IN_CLUNKS2;
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NextRateSelect = RTC_RATE_SELECT2;
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} else {
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NewTimeIncrement = RTC_PERIOD_IN_CLUNKS1;
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NextRateSelect = RTC_RATE_SELECT1;
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}
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HalpNextRateSelect = NextRateSelect;
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HalpNewTimeIncrement = NewTimeIncrement;
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KeLowerIrql(OldIrql);
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return NewTimeIncrement;
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}
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VOID
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HalpInitializeHAERegisters(
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VOID
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)
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/*++
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Routine Description:
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This function initializes the HAE registers in the EPIC/APECS chipset.
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|
It also register the holes in the PCI memory space if any.
|
|
|
|
Arguments:
|
|
|
|
none
|
|
|
|
Return Value:
|
|
|
|
none
|
|
|
|
--*/
|
|
{
|
|
//
|
|
// Set HAXR1 to 0, which means no address extension
|
|
//
|
|
|
|
WRITE_EPIC_REGISTER (&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr1, 0);
|
|
|
|
//
|
|
// We set HAXR2 to MB. Which means we have the following
|
|
// PCI IO addresses:
|
|
// 0 to 64KB VALID. HAXR2 Not used in address translation
|
|
// 64K to 16MB VALID. HAXR2 is used in the address translation
|
|
//
|
|
|
|
WRITE_EPIC_REGISTER ( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr2, 0);
|
|
|
|
//
|
|
// Report that the apecs mapping to the Io subsystem
|
|
//
|
|
|
|
HalpRegisterAddressUsage (&EB64pPCIMemorySpace);
|
|
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpResetHAERegisters(
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function resets the HAE registers in the EPIC/APECS chipset to 0.
|
|
This is routine called during a shutdown so that the prom
|
|
gets a predictable environment.
|
|
|
|
Arguments:
|
|
|
|
none
|
|
|
|
Return Value:
|
|
|
|
none
|
|
|
|
--*/
|
|
{
|
|
WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr1, 0 );
|
|
WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr2, 0 );
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpGetMachineDependentErrorFrameSizes(
|
|
PULONG RawProcessorSize,
|
|
PULONG RawSystemInfoSize
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function returns the size of the system specific structures.
|
|
|
|
|
|
Arguments:
|
|
|
|
RawProcessorSize - Pointer to a buffer that will receive the
|
|
size of the processor specific error information buffer.
|
|
|
|
RawSystemInfoSize - Pointer to a buffer that will receive the
|
|
size of the system specific error information buffer.
|
|
|
|
Return Value:
|
|
|
|
none
|
|
|
|
--*/
|
|
{
|
|
*RawProcessorSize = sizeof(PROCESSOR_EV4_UNCORRECTABLE);
|
|
*RawSystemInfoSize = sizeof(APECS_UNCORRECTABLE_FRAME);
|
|
return;
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpGetSystemInfo(SYSTEM_INFORMATION *SystemInfo)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function fills in the System information.
|
|
|
|
|
|
Arguments:
|
|
|
|
SystemInfo - Pointer to the SYSTEM_INFORMATION buffer that needs
|
|
to be filled in.
|
|
|
|
Return Value:
|
|
|
|
none
|
|
|
|
--*/
|
|
{
|
|
char systemtype[] = "eb64p";
|
|
EXTENDED_SYSTEM_INFORMATION FwExtSysInfo;
|
|
|
|
|
|
VenReturnExtendedSystemInformation(&FwExtSysInfo);
|
|
|
|
RtlCopyMemory(SystemInfo->FirmwareRevisionId,
|
|
FwExtSysInfo.FirmwareVersion,
|
|
16);
|
|
|
|
RtlCopyMemory(SystemInfo->SystemType,systemtype, 8);
|
|
|
|
SystemInfo->ClockSpeed =
|
|
((1000 * 1000) + (PCR->CycleClockPeriod >> 1)) / PCR->CycleClockPeriod;
|
|
|
|
SystemInfo->SystemRevision = PCR->SystemRevision;
|
|
|
|
RtlCopyMemory(SystemInfo->SystemSerialNumber,
|
|
PCR->SystemSerialNumber,
|
|
16);
|
|
|
|
SystemInfo->SystemVariant = PCR->SystemVariant;
|
|
|
|
|
|
SystemInfo->PalMajorVersion = PCR->PalMajorVersion;
|
|
SystemInfo->PalMinorVersion = PCR->PalMinorVersion;
|
|
|
|
SystemInfo->OsRevisionId = VER_PRODUCTBUILD;
|
|
|
|
//
|
|
// For now fill in dummy values.
|
|
//
|
|
SystemInfo->ModuleVariant = 1UL;
|
|
SystemInfo->ModuleRevision = 1UL;
|
|
SystemInfo->ModuleSerialNumber = 0;
|
|
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
HalpInitializeUncorrectableErrorFrame (
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function Allocates an Uncorrectable Error frame for this
|
|
system and initializes the frame with certain constant/global
|
|
values.
|
|
|
|
This is routine called during machine dependent system
|
|
Initialization.
|
|
|
|
Arguments:
|
|
|
|
none
|
|
|
|
Return Value:
|
|
|
|
none
|
|
|
|
--*/
|
|
{
|
|
PROCESSOR_EV4_UNCORRECTABLE processorFrame;
|
|
|
|
//
|
|
// If the Uncorrectable error buffer is not set then simply return
|
|
//
|
|
if(PUncorrectableError == NULL)
|
|
return;
|
|
|
|
PUncorrectableError->Signature = ERROR_FRAME_SIGNATURE;
|
|
|
|
PUncorrectableError->FrameType = UncorrectableFrame;
|
|
|
|
//
|
|
// ERROR_FRAME_VERSION is define in errframe.h and will
|
|
// change as and when there is a change in the errframe.h.
|
|
// This Version number helps the service, that reads this
|
|
// information from the dumpfile, to check if it knows about
|
|
// this frmae version type to decode. If it doesn't know, it
|
|
// will dump the entire frame to the EventLog with a message
|
|
// "Error Frame Version Mismatch".
|
|
//
|
|
|
|
PUncorrectableError->VersionNumber = ERROR_FRAME_VERSION;
|
|
|
|
//
|
|
// The sequence number will always be 1 for Uncorrectable errors.
|
|
//
|
|
|
|
PUncorrectableError->SequenceNumber = 1;
|
|
|
|
//
|
|
// The PerformanceCounterValue field is not used for Uncorrectable
|
|
// errors.
|
|
//
|
|
|
|
PUncorrectableError->PerformanceCounterValue = 0;
|
|
|
|
//
|
|
// We will fill in the UncorrectableFrame.SystemInfo here.
|
|
//
|
|
|
|
HalpGetSystemInfo(&PUncorrectableError->UncorrectableFrame.System);
|
|
|
|
PUncorrectableError->UncorrectableFrame.Flags.SystemInformationValid = 1;
|
|
|
|
return;
|
|
}
|