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413 lines
10 KiB
413 lines
10 KiB
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: fpbt445.c $
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* $Revision: 1.9 $
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* $Date: 1996/05/14 02:32:18 $
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* $Locker: $
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*
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* This file contains references to registers in the display controller chip
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* known as the DCC. This chip control's vram setup and works in conjunction
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* with the ram dac which, in this case is a Brooktree Bt485.
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*
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*/
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#include "halp.h"
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#include "phsystem.h"
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#include "fpio.h"
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#include "fpDcc.h"
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#include "fpBt445.h"
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VOID
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HalpSetupBt445(
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ULONG Mode,
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ULONG VramWidth
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)
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/*++
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Routine Description:
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This routine initializes the display hardware for 640x480 in preparation
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for HalDisplayString(). This means that either we are booting up or
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dealing with the blue screen of death. We should really change this to
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a higher resolution ASAP. [ged]
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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ULONG i;
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ULONG modeIndex;
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//
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// BT445 Mask value
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//
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// The order of entries must match btTab
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//
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UCHAR btMask[30][3] = {
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{6,0x05,0x3f},
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{6,0x06,0xcf},
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{6,0x07,0x00},
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{2,0x06,0x7f},
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{6,0x0a,0xbb},
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{6,0x0d,0x00},
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{5,0x00,0x00},
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{5,0x08,0x00},
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{5,0x10,0x00},
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{6,0x09,0x00},
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{6,0x01,0xdf},
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{6,0x02,0xbf},
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{5,0x1a,0x0f},
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{5,0x22,0x03},
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{6,0x0f,0x00},
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{6,0x03,0x3f},
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{6,0x0b,0x3f},
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{5,0x01,0x00},
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{5,0x09,0x00},
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{5,0x11,0x00},
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{2,0x05,0x00},
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{2,0x04,0x00},
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{5,0x18,0x00},
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{5,0x19,0x00},
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{5,0x1b,0x0f},
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{5,0x20,0x00},
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{5,0x21,0x00},
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{5,0x23,0x03},
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{6,0x0e,0x00},
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{6,0x08,0x1c}
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};
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// BT445 Address register
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// address (index)
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// register
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// 2 = BT445 Group 0 Register
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// 5 = BT445 Config Register
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// 6 = BT445 Group 1 Register
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// value
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typedef struct {
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UCHAR reg;
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UCHAR addr;
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UCHAR value;
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} BTTAB; // [rdl:01.03.95]
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// [rdl:01.03.95]
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BTTAB btTab[3 /* 32/64/128 bit vram */][2 /* mode 0 or 15 */][30] = {
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// 32 bit VRAM width
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{
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// Mode 0 - 640X480 8 bit 72Hz
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{
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{6,0x05,0x2c},
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{6,0x06,0x84},
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{6,0x07,0x84},
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{2,0x06,0x00},
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{6,0x0a,0x00},
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{6,0x0d,0x08},
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{5,0x00,0x07},
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{5,0x08,0x07},
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{5,0x10,0x07},
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{6,0x09,0x40},
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{6,0x01,0x40},
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{6,0x02,0x00},
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{5,0x1a,0x00},
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{5,0x22,0x00},
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{6,0x0f,0x01},
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{6,0x03,0x03},
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{6,0x0b,0x03},
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{5,0x01,0x08},
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{5,0x09,0x08},
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{5,0x11,0x08},
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{2,0x05,0x00},
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{2,0x04,0xff},
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{5,0x18,0x00},
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{5,0x19,0x01},
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{5,0x1b,0x00},
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{5,0x20,0x00},
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{5,0x21,0x01},
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{5,0x23,0x00},
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{6,0x0e,0x00},
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{6,0x08,0x04}
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},
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// Mode 15 - 1024X768 8 bit 60Hz
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{
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{6,0x05,0x37},
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{6,0x06,0x45},
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{6,0x07,0x84},
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{2,0x06,0x00},
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{6,0x0a,0x00},
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{6,0x0d,0x08},
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{5,0x00,0x07},
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{5,0x08,0x07},
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{5,0x10,0x07},
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{6,0x09,0x40},
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{6,0x01,0x40},
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{6,0x02,0x00},
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{5,0x1a,0x00},
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{5,0x22,0x00},
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{6,0x0f,0x01},
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{6,0x03,0x03},
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{6,0x0b,0x03},
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{5,0x01,0x08},
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{5,0x09,0x08},
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{5,0x11,0x08},
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{2,0x05,0x00},
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{2,0x04,0xff},
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{5,0x18,0x00},
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{5,0x19,0x01},
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{5,0x1b,0x00},
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{5,0x20,0x00},
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{5,0x21,0x01},
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{5,0x23,0x00},
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{6,0x0e,0x00},
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{6,0x08,0x04}
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}
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},
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// 64 bit VRAM width
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{
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// Mode 0 - 640X480 8 bit 72Hz
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{
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{6,0x05,0x2c},
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{6,0x06,0x84},
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{6,0x07,0x84},
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{2,0x06,0x00},
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{6,0x0a,0x80},
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{6,0x0d,0x08},
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{5,0x00,0x07},
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{5,0x08,0x07},
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{5,0x10,0x07},
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{6,0x09,0x00},
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{6,0x01,0x40},
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{6,0x02,0x00},
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{5,0x1a,0x00},
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{5,0x22,0x00},
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{6,0x0f,0x01},
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{6,0x03,0x07},
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{6,0x0b,0x07},
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{5,0x01,0x08},
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{5,0x09,0x08},
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{5,0x11,0x08},
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{2,0x05,0x00},
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{2,0x04,0xff},
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{5,0x18,0x00},
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{5,0x19,0x01},
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{5,0x1b,0x00},
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{5,0x20,0x00},
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{5,0x21,0x01},
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{5,0x23,0x00},
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{6,0x0e,0x00},
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{6,0x08,0x04}
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},
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// Mode 15 - 1024X768 8 bit 60Hz
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{
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{6,0x05,0x37},
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{6,0x06,0x45},
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{6,0x07,0x84},
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{2,0x06,0x00},
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{6,0x0a,0x80},
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{6,0x0d,0x08},
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{5,0x00,0x07},
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{5,0x08,0x07},
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{5,0x10,0x07},
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{6,0x09,0x00},
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{6,0x01,0x40},
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{6,0x02,0x00},
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{5,0x1a,0x00},
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{5,0x22,0x00},
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{6,0x0f,0x01},
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{6,0x03,0x07},
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{6,0x0b,0x07},
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{5,0x01,0x08},
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{5,0x09,0x08},
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{5,0x11,0x08},
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{2,0x05,0x00},
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{2,0x04,0xff},
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{5,0x18,0x00},
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{5,0x19,0x01},
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{5,0x1b,0x00},
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{5,0x20,0x00},
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{5,0x21,0x01},
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{5,0x23,0x00},
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{6,0x0e,0x00},
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{6,0x08,0x04}
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}
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},
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// 128 bit VRAM width
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{
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// Mode 0 - 640X480 8 bit 72Hz
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{
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{6,0x05,0x2c},
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{6,0x06,0x84},
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{6,0x07,0x84},
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{2,0x06,0x00},
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{6,0x0a,0x80},
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{6,0x0d,0x08},
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{5,0x00,0x07},
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{5,0x08,0x07},
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{5,0x10,0x07},
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{6,0x09,0x00},
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{6,0x01,0x40},
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{6,0x02,0x00},
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{5,0x1a,0x00},
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{5,0x22,0x00},
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{6,0x0f,0x01},
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{6,0x03,0x07},
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{6,0x0b,0x07},
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{5,0x01,0x08},
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{5,0x09,0x08},
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{5,0x11,0x08},
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{2,0x05,0x00},
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{2,0x04,0xff},
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{5,0x18,0x00},
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{5,0x19,0x01},
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{5,0x1b,0x00},
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{5,0x20,0x00},
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{5,0x21,0x01},
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{5,0x23,0x00},
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{6,0x0e,0x00},
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{6,0x08,0x04}
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},
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// Mode 15 - 1024X768 8 bit 60Hz
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{
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{6,0x05,0x37},
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{6,0x06,0x45},
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{6,0x07,0x84},
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{2,0x06,0x00},
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{6,0x0a,0x80},
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{6,0x0d,0x08},
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{5,0x00,0x07},
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{5,0x08,0x07},
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{5,0x10,0x07},
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{6,0x09,0x00},
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{6,0x01,0x40},
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{6,0x02,0x00},
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{5,0x1a,0x00},
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{5,0x22,0x00},
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{6,0x0f,0x01},
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{6,0x03,0x07},
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{6,0x0b,0x07},
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{5,0x01,0x08},
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{5,0x09,0x08},
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{5,0x11,0x08},
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{2,0x05,0x00},
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{2,0x04,0xff},
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{5,0x18,0x00},
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{5,0x19,0x01},
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{5,0x1b,0x00},
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{5,0x20,0x00},
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{5,0x21,0x01},
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{5,0x23,0x00},
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{6,0x0e,0x00},
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{6,0x08,0x04}
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}
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}
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};
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//
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// Setup the RAMDAC (Bt445)
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//
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// go table driven [rdl:01.03.95]
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//
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modeIndex = (Mode) ? 1 : 0; // if not mode 0, then make it mode 15.
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for (i = 0; i < sizeof(btTab[0][0])/sizeof(BTTAB); i++) {
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BTTAB tab = btTab[VramWidth][modeIndex][i];
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UCHAR value = tab.value;
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WRITE_REGISTER_UCHAR((PUCHAR)HalpIoControlBase + BT445_ADDRESS, tab.addr);
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FireSyncRegister();
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if (tab.reg == btMask[i][0] && tab.addr == btMask[i][1]) {
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if (btMask[i][2]) {
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value = READ_REGISTER_UCHAR((PUCHAR)HalpIoControlBase + BT445_ADDRESS + tab.reg);
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value &= ~btMask[i][2];
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value |= btMask[i][2] & tab.value;
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}
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} else {
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//
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// btMask is out of order with respect to btTab
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//
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KeBugCheck(HAL_INITIALIZATION_FAILED);
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}
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WRITE_REGISTER_UCHAR((PUCHAR)HalpIoControlBase + BT445_ADDRESS + tab.reg, value);
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FireSyncRegister();
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}
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//
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// ...and program the color lookup table with "NT" colors
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// starting pixel address for loading RGB values:
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//
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rRamDacAddr = 0;
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FireSyncRegister();
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//
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// load the red, green, and blue data for pixel 0:
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//
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rDacPrimeLut = 0x00;
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FireSyncRegister();
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rDacPrimeLut = 0x00;
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FireSyncRegister();
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rDacPrimeLut = 0x00;
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FireSyncRegister();
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//
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// load the red, green, and blue data for pixel 1: ( this gives NT
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// the characteristice BLUE screen for booting )
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//
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rDacPrimeLut = 0x00;
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FireSyncRegister();
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rDacPrimeLut = 0x00;
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FireSyncRegister();
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rDacPrimeLut = 0xff;
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FireSyncRegister();
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for (i=2; i<=0xff; i++) {
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/* A grey ramp with entry 255 white */
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rDacPrimeLut = (UCHAR) i;
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rDacPrimeLut = (UCHAR) i;
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rDacPrimeLut = (UCHAR) i;
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FireSyncRegister();
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}
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return;
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} // Init Vram
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ULONG
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HalpSetPixelColorMap( ULONG Color, ULONG Pixel )
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{
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UCHAR Red, Green, Blue, Control;
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//
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// set the display to red while in phase 0:
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//
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rRamDacAddr = (UCHAR) ( Pixel & 0x000000ff);
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FireSyncRegister();
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Control = (UCHAR) ( ( Color >> 24 ) & 0x000000ff );
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Red = (UCHAR) ( ( Color >> 16 ) & 0x000000ff );
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Green = (UCHAR) ( ( Color >> 8 ) & 0x000000ff );
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Blue = (UCHAR) ( Color & 0x000000ff );
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//
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// load the red, green, and blue data for pixel 1:
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// ( this is the normal NT BLUE boot screen )
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//
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rDacPrimeLut = Red; // set this pixel to no red ...
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FireSyncRegister();
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rDacPrimeLut = Green; // set this pixel to no green ...
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FireSyncRegister();
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rDacPrimeLut = Blue; // set this pixel to max blue.
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FireSyncRegister();
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return(0);
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}
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