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180 lines
4.8 KiB
180 lines
4.8 KiB
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: fpbt445.h $
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* $Revision: 1.7 $
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* $Date: 1996/01/11 07:05:32 $
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* $Locker: $
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*
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* This file contains references to registers in the BrookTree Bt445 RamDac.
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*
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*/
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#ifndef FPBT445_H
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#define FPBT445_H
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/*
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** The Bt445 organizes it's registers into a complex index based arrangement.
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** The final data registers are actually accessed via some control bits which
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** show up memory mapped. However, since each control address can access
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** several registers, the register desired must be specified through the Bt445
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** index register. For example, if you want to read the ID value of the chip,
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** you must write the id register value ( 0x00 ) to the Bt445 address ( index ).
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** Then you must read the address that corresponds to control register 2.
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**
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*/
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//
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// defines for access to control register 0 ( c bits = 000 )
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// Use rRamDacAddr to access the Bt445 address register
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//
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#define BT_Address 0x00 // index register into the Bt445.
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//
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// defines for access to control register 1 ( c bits = 001 )
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// Use rDacPrimeLut to access the primary color palette register
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// NOTE: This register requires MODULO 3 loading and reading
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//
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//
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// defines for access to control register 2 ( c bits = 010 )
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// use rRamDacCntl to access
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//
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#define DAC_ID_REG 0x00 //
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#define DAC_REVISION_REG 0x01
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#define DAC_READ_ENABLE 0x04
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#define DAC_BLINK_ENABLE 0x05
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#define DAC_COMMAND_REG0 0x06
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#define DAC_TEST_REG0 0x07
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//
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// defines for access to control register 3 ( c bits = 011 )
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// use rDacOvlayLut to access the overlay color palette
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// NOTE: This register requires MODULO 3 loading and reading
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//
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//
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// defines for access to control register 5 ( c bits = 101 )
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// use rDacPixelBit to access the rgb pixel layout register
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//
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#define RED_MSB_POSITION 0x00
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#define RED_WIDTH_CNTL 0x01
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#define RED_DISPLAY_ENBL 0x02
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#define RED_BLINK_ENBL 0x03
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#define GREEN_MSB_POSITION 0x08
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#define GREEN_WIDTH_CNTL 0x09
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#define GREEN_DISPLAY_ENBL 0x0A
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#define GREEN_BLINK_ENBL 0x0B
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#define BLUE_MSB_POSITION 0x10
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#define BLUE_WIDTH_CNTL 0x11
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#define BLUE_DISPLAY_ENBL 0x12
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#define BLUE_BLINK_ENBL 0x13
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#define OVRLY_MSB_POSITION 0x18
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#define OVRLY_WIDTH_CNTL 0x19
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#define OVRLY_DISPLAY_ENBL 0x1A
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#define OVRLY_BLINK_ENBL 0x1B
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#define CURSOR_MSB_POSITION 0x20
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#define CURSOR_WIDTH_CNTL 0x21
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#define CURSOR_DISPLAY_ENBL 0x22
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#define CURSOR_BLINK_ENBL 0x23
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//
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// defines for access to control register 6 ( c bits = 110 )
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// use rDacPixelClks to access
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//
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#define TEST_REG1 0x00
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#define COMMAND_REG1 0x01
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#define DIGI_OUT_CNTL 0x02
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#define VIDCLK_CYCLE 0x03
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#define PIXEL_PLL_RATE0 0x05
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#define PIXEL_PLL_RATE1 0x06
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#define PLL_CONTROL 0x07
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#define PIXEL_LOAD_CNTL 0x08
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#define PIXEL_PORT_START 0x09
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#define PIXEL_FORMAT_CNTL 0x0A
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#define MPX_RATE_REG 0x0B
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#define SIG_ANLYS_REG 0x0C
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#define PIXEL_DEPTH_CNTL 0x0D
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#define PALETTE_BYPASS_POS 0x0E
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#define PALETTE_BYPASS_WIDTH 0x0F
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//
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// defines for access to control register 7 ( c bits = 111 )
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// use rRamDacCursor to access the cursor color register
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// NOTE: This register requires MODULO 3 loading and reading
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//
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#define CURSOR_CLR0 0x00
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#define CURSOR_CLR1 0x01
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#define CURSOR_CLR2 0x02
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#define CURSOR_CLR3 0x03
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/*
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**
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**.................... Bit Field Definitions........................
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**
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*/
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//
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// Command Register 0 bit masks:
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//
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#define USE_PALETTE 0x40 // use color palette not overlay color 0
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//
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// These defines cover TWO bits: bit positions 4 and 5
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//
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#define BLINK_16ON_48OFF 0x00
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#define BLINK_16ON_16OFF 0x10
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#define BLINK_32ON_32OFF 0x20
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#define BLINK_64ON_64OFF 0x30
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#define ENBL_OVRLY0_BLINK 0x04
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#define ENBL_OVRLY1_BLINK 0x08
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#define ENBL_OVRLY0_DSPLY 0x02
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#define ENBL_OVRLY1_DSPLY 0x01
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//
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// COMMAND_REG1: Bit fields
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//
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#define ENABLE_GREEN_SYNC 0x80 // generate sync on the IOG output
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#define IRE75_PEDESTAL 0x40 // generate a blank pedestal of 7.5 IRE
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#define NORMAL_POWER_OP 0x00 // normal operations ( i.e. no pwr dwn )
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#define PWR_OFF_DACS 0x08 // Turn off DACs. functionally still ops
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#define DAC_RAM_OFF 0x10 // Dac and Ram off: no functions out
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#define DAC_RAM_CLKS_OFF 0x18 // turn off clocks too
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#define RIGHT_JSTFY_PIXBITS 0x04 // right justify pixels and zero extend
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#define ENABLE_SIG_ANLYS 0x02 // turn on SAR
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#define RESET_PIPE_DEPTH 0x01
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// Pixel Timing Register: Field definitions:
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//
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/*
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** Pixel Format Control Fields ( PIXEL_FORMAT_CNTL register )
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**
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*/
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#define UNPACK_LSB_FIRST 0x80
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#define ENABLE_CURSOR 0x20
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#define ENABLE_CURSOR_COLOR0 0x10
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#define ENABLE_OVERLAY 0x08
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#define USE_COLOR_PALETTE 0x00
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#define BYPASS_COLOR_PALETTE 0x01
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#define USE_INPUT_PIXEL_FIELD 0x02
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/*
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** Pixel PLL Rate Register 0
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*/
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//
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// Prototype Declarations
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//
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VOID HalpSetupBt445( ULONG, ULONG );
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ULONG HalpSetPixelColorMap( ULONG Color, ULONG Pixel );
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#endif
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