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226 lines
6.1 KiB
226 lines
6.1 KiB
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: fpdcc.c $
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* $Revision: 1.12 $
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* $Date: 1996/01/11 07:06:05 $
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* $Locker: $
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*
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* This file contains references to registers in the display controller chip
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* known as the DCC. This chip control's vram setup and works in conjunction
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* with the ram dac which, in this case is a Brooktree Bt485.
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*
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*/
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#include "halp.h"
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#include "phsystem.h"
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#include "fpio.h"
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#include "fpDcc.h"
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#include "fpbt445.h"
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VOID
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HalpSetupDCC(
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ULONG Mode,
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ULONG VramWidth
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);
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/*++
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Routine Description: VOID HalpSetupDCC()
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This routine initializes the display hardware for 640x480 in preparation
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for HalDisplayString(). This means that either we are booting up or
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dealing with the blue screen of death. We should really change this to
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a higher resolution ASAP. [ged]
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Arguments:
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None.
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Return Value:
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None.
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--*/
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VOID
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HalpSetupDCC(
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ULONG Mode,
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ULONG VramWidth
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)
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{
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LONG modeIndex;
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LONG i;
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//
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// DCC Config A
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//
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UCHAR configA[NUMBER_OF_VRAM_WIDTH_TYPES] = {
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A_1to1_64BitDac | HSYNC_ENABLE | VSYNC_ENABLE | CSYNC_ENABLE,
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A_1to1_64BitDac | HSYNC_ENABLE | VSYNC_ENABLE | CSYNC_ENABLE,
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A_2to1_64BitDac | HSYNC_ENABLE | VSYNC_ENABLE | CSYNC_ENABLE
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};
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// [rdl:01.03.95]
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typedef struct {
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UCHAR reg;
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UCHAR value;
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} DCCTAB;
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// [rdl:01.03.95]
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DCCTAB DCCtab[3 /* 32/64/128 bit vram */][2 /* mode 0 or 15 */][13] = {
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// 32 bit VRAM width
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{
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// [0] Mode 0 - 640X480 8 bit 72Hz
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{
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{HZNTL_COUNT_L,0xcf},
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{HZNTL_COUNT_H,0x00},
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{VERT_COUNT_L,0x07},
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{VERT_COUNT_H,0x02},
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{HZNTL_SYNC_STOP,0x09},
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{HZNTL_BLK_STP_L,0x29},
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{HZNTL_BLK_STP_H,0x00},
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{HZNTL_DTA_STP_L,0xc9},
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{HZNTL_DTA_STP_H,0x00},
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{VERT_SYNC_STOP,0x02},
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{VERT_BLK_STOP,0x1e},
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{VERT_DTA_STP_L,0xfe},
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{VERT_DTA_STP_H,0x01}
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},
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// [1] Mode 15 - 1024X768 8 bit 60Hz
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{
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{HZNTL_COUNT_L,0x4f},
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{HZNTL_COUNT_H,0x01},
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{VERT_COUNT_L,0x25},
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{VERT_COUNT_H,0x03},
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{HZNTL_SYNC_STOP,0x21},
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{HZNTL_BLK_STP_L,0x49},
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{HZNTL_BLK_STP_H,0x00},
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{HZNTL_DTA_STP_L,0x49},
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{HZNTL_DTA_STP_H,0x01},
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{VERT_SYNC_STOP,0x05},
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{VERT_BLK_STOP,0x22},
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{VERT_DTA_STP_L,0x22},
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{VERT_DTA_STP_H,0x03},
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}
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},
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// 64 bit VRAM width
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{
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// [0] Mode 0 - 640X480 8 bit 72Hz
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{
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{HZNTL_COUNT_L,0x67},
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{HZNTL_COUNT_H,0x00},
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{VERT_COUNT_L,0x07},
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{VERT_COUNT_H,0x02},
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{HZNTL_SYNC_STOP,0x04},
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{HZNTL_BLK_STP_L,0x14},
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{HZNTL_BLK_STP_H,0x00},
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{HZNTL_DTA_STP_L,0x64},
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{HZNTL_DTA_STP_H,0x00},
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{VERT_SYNC_STOP,0x02},
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{VERT_BLK_STOP,0x1e},
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{VERT_DTA_STP_L,0xfe},
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{VERT_DTA_STP_H,0x01}
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},
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// [1] Mode 15 - 1024X768 8 bit 60Hz
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{
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{HZNTL_COUNT_L,0xa7},
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{HZNTL_COUNT_H,0x00},
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{VERT_COUNT_L,0x25},
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{VERT_COUNT_H,0x03},
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{HZNTL_SYNC_STOP,0x10},
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{HZNTL_BLK_STP_L,0x24},
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{HZNTL_BLK_STP_H,0x00},
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{HZNTL_DTA_STP_L,0xa4},
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{HZNTL_DTA_STP_H,0x00},
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{VERT_SYNC_STOP,0x05},
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{VERT_BLK_STOP,0x22},
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{VERT_DTA_STP_L,0x22},
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{VERT_DTA_STP_H,0x03},
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}
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},
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// 128 bit VRAM width
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{
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// [0] Mode 0 - 640X480 8 bit 72Hz
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{
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{HZNTL_COUNT_L,0x67},
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{HZNTL_COUNT_H,0x00},
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{VERT_COUNT_L,0x07},
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{VERT_COUNT_H,0x02},
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{HZNTL_SYNC_STOP,0x04},
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{HZNTL_BLK_STP_L,0x14},
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{HZNTL_BLK_STP_H,0x00},
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{HZNTL_DTA_STP_L,0x64},
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{HZNTL_DTA_STP_H,0x00},
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{VERT_SYNC_STOP,0x02},
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{VERT_BLK_STOP,0x1e},
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{VERT_DTA_STP_L,0xfe},
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{VERT_DTA_STP_H,0x01}
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},
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// [1] Mode 15 - 1024X768 8 bit 60Hz
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{
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{HZNTL_COUNT_L,0xa7},
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{HZNTL_COUNT_H,0x00},
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{VERT_COUNT_L,0x25},
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{VERT_COUNT_H,0x03},
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{HZNTL_SYNC_STOP,0x10},
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{HZNTL_BLK_STP_L,0x24},
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{HZNTL_BLK_STP_H,0x00},
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{HZNTL_DTA_STP_L,0xa4},
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{HZNTL_DTA_STP_H,0x00},
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{VERT_SYNC_STOP,0x05},
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{VERT_BLK_STOP,0x22},
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{VERT_DTA_STP_L,0x22},
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{VERT_DTA_STP_H,0x03},
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}
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}
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};
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//
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// Disable all counters and state machines before we go messing around.
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//
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rDccIndex = dccConfigB;
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FireSyncRegister();
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rDccData = DCC_HALT_CLK;
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FireSyncRegister();
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HalpSetupBt445(Mode, VramWidth);
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//
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// Setup the DCC
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//
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rDccIndex = dccIntReg;
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FireSyncRegister();
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rDccData = 0x00; // Clear the interrupt bit ( bit 0 )
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FireSyncRegister();
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rDccIndex = dccTimingA;
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FireSyncRegister();
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rDccData = 0x07; // delay syncs by 7 DispClk cycles
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FireSyncRegister();
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rDccIndex = dccConfigA;
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FireSyncRegister();
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rDccData = configA[VramWidth];
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FireSyncRegister();
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#define DCC_STORE(reg,val) { \
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WRITE_REGISTER_UCHAR((PUCHAR)HalpIoControlBase + DCC_INDEX, reg); \
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WRITE_REGISTER_UCHAR((PUCHAR)HalpIoControlBase + DCC_DATA, val); \
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}
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// go table driven [rdl:01.03.95]
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modeIndex = (Mode) ? 1 : 0; // if not mode 0, then make it mode 15.
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for (i = 0; i < sizeof(DCCtab[0][0])/sizeof(DCCTAB); i++) {
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DCCTAB tab = DCCtab[VramWidth][modeIndex][i];
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DCC_STORE(tab.reg, tab.value);
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}
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rDccIndex = dccConfigB; // Turn on counters, *DO LAST*
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FireSyncRegister();
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rDccData = 0x00;
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FireSyncRegister();
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return;
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} // HalpSetupDCC
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