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142 lines
4.8 KiB
142 lines
4.8 KiB
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* (Do Not Distribute without permission)
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*
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* $RCSfile: fpdcc.h $
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* $Revision: 1.11 $
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* $Date: 1996/01/11 07:06:16 $
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* $Locker: $
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*
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* This file contains references to registers in the display controller chip
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* known as the DCC. This chip control's vram setup and works in conjunction
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* with the ram dac which, in this case is a Brooktree Bt445.
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*
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*/
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#ifndef FPDCC_H
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#define FPDCC_H
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//
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// Prototype declarations for routines in fpDcc.c
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// The dcc registers are not memory mapped but are indexed map through the
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// dcc Index register. To access any dcc specific register, write the register
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// value to the index register and either read or write data through the data
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// register. See fpio.h for the macros to write to these registers
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//
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// register and address offset
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//-----------------------------
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//
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#define dccIndex DCC_INDEX
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#define dccID 0x00 // ID register
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#define dccMonId 0x01 // Monitor and Panel ID
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#define dccGpioA 0x02 // General Purpose I/O register A
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#define dccIntReg 0x03 // Interrupt Status
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#define dccPLL 0x04 // PLL Interface Register
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#define dccTimingA 0x05 // Timing Register A
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#define dccConfigA 0x06 // Configuration Register A
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#define dccConfigB 0x07 // Configuration Register B
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#define dccHCntLow 0x08 // Hoizontal Count Low
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#define dccHCntHigh 0x09 // Hoizontal Count High
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#define dccVCntLow 0x0A // Vertical Count Low
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#define dccVCntHigh 0x0B // Vertical Count High
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#define dccHSyncStop 0x0C // Hoizontal Sync Stop
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#define dccHBlankStopLow 0x0D // Horizontal Blank Stop low
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#define dccHBlankStopHigh 0x0E // Horizontal Blank Stop High
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#define dccHDataStopLow 0x0F // Horizontal Data Stop Low
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#define dccHDataStopHigh 0x10 // Horizontal Data Stop High
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#define dccVSyncStop 0x11 // Vertical Sync Stop
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#define dccVBlankStop 0x12 // Vertical Blank Stop
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#define dccVDataStopLow 0x13 // Vertical Data Stop Low
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#define dccVDataStopHigh 0x14 // Vertical Data Stop High
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#define dccCSynicStartLow 0x15 // Composite Sync Start Low
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#define dccCSyncStartHigh 0x16 // Composite Sync Start High
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#define dccLineStart 0x17 // Line Start
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#define dccLineStop 0x18 // Line Stop
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#define dccFrameStart 0x19 // Frame Start
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#define dccFrameStop 0x1a // Frame Stop
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#define dccIntTriggerLow 0x1B // Interrupt Trigger Low
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#define dccIntTriggerHigh 0x1C // Interrupt Trigger High
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#define dccTimingB 0x1D // Timing Register B
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#define dccGpioB 0x1E // General Purpose I/O register B
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//
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// 0x1E - 0x3F reserved;
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//
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//
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// Inidividual bit mappings for register use:
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#define INT_BIT 0x01 // LSB of Interrupt Register: dccIntReg
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#define PLL_CLK 0x01 // PLL clock bit in Pll Interface: dccPLL
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#define PLL_DATA 0x02 // Data Bit for the PLL port.
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#define PLL_WnotR 0x04 // this bit activates the Pll data driver.
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#define HV_SYNC_DELAY 0x0f
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#define CSYNC_DELAY 0xf0
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//
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// Configuration Register A
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//
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#define HSYNC_ENABLE 0x01 // enable Horizontal Sync pulse
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#define VSYNC_ENABLE 0x02 // enable Vertical Sync pulse
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#define CSYNC_ENABLE 0x04 // enable Composite Sync pulse
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#define FRAME_ENABLE 0x08 // enable Frame pulse
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#define LINE_ENABLE 0x10 // enable Line pulse
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#define A_1to1_32BitDac 0x00 // 1:1 mux mode, frequency = DispClk
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#define AB_2to1_32BitDac 0x20 // 2:1 mux mode, frequency = 1/2DispClk
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#define A_1to1_64BitDac 0x80 // 1:1 mux, 64 bit Data width, f=DispClk
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#define A_2to1_32BitDac 0xA0 // 2:1 mux, 32 bit width, f=1/2(DispClk)
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#define A_2to1_64BitDac 0xC0 // 2:1 mux, 64 bit width, f=1/2(DispClk)
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#define A_4to1_32BitDac 0xE0 // 4:1 mux, 32 bit width, f=1/4(DispClk)
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//
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// Configuration Register B
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//
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#define HSYNC_ACTV_HIGH 0x01 // Active High state for Horizontal Sync
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#define VSYNC_ACTV_HIGH 0x02 // Active High state for Vertical Sync
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#define CSYNC_ACTV_HIGH 0x04 // Active High state for Composite Sync
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#define FRAME_ACTV_HIGH 0x08 // Active High state for Frame Pulse
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#define LINE_ACTV_HIGH 0x10 // Active High state for Line Pulse
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#define BLANK_ACTV_HIGH 0x20 // Active High state for Blanking Pulse
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#define DCC_HALT_CLK 0x80 // Disables and Resets all counters and state
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// machines. Xbus interface is still active.
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// DCC Definitions
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#define INT_STATUS 0x03
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#define PLL_INTERFACE 0x04
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#define TIMING_A 0x05
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#define CONFIG_A 0x06
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#define CONFIG_B 0x07
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#define HZNTL_COUNT_L 0x08
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#define HZNTL_COUNT_H 0x09
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#define VERT_COUNT_L 0x0a
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#define VERT_COUNT_H 0x0b
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#define HZNTL_SYNC_STOP 0x0c
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#define HZNTL_BLK_STP_L 0x0d
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#define HZNTL_BLK_STP_H 0x0e
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#define HZNTL_DTA_STP_L 0x0f
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#define HZNTL_DTA_STP_H 0x10
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#define VERT_SYNC_STOP 0x11
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#define VERT_BLK_STOP 0x12
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#define VERT_DTA_STP_L 0x13
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#define VERT_DTA_STP_H 0x14
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#define GPIO_B 0x1e
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//
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// VRAM width list.
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//
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typedef enum _DCC_VRAM_WIDTH {
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VRAM_32BIT = 0,
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VRAM_64BIT,
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VRAM_128BIT,
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NUMBER_OF_VRAM_WIDTH_TYPES
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} DCC_VRAM_WIDTH;
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#endif
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