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230 lines
6.6 KiB
230 lines
6.6 KiB
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: fpio.h $
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* $Revision: 1.9 $
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* $Date: 1996/01/11 07:06:50 $
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* $Locker: $
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*
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* This file contains references to registers in I/O space only. That is any
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* access to the ISA or PCI space ( or any future additions ) are contained in
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* this file. Access to device registers that do not lie in I/O space should
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* be defined in the file fpreg.h
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*
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*/
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#ifndef FPIO_H
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#define FPIO_H
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//
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// Define macros for handling accesses to io-space:
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//
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// HalpIoControlBase is extern'd in pxhalp.h which is included by halp.h
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#define _IOBASE ((PUCHAR)HalpIoControlBase)
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#define _IOREG(_OFFSET) (*(volatile UCHAR * const)((_IOBASE + (_OFFSET))))
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#define _IOADDR(_OFFSET) ((_IOBASE + (_OFFSET)))
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#define _PCIOBASE ((PUCHAR)HalpPciConfigBase)
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#define _PCIOREG(_OFFSET) (*(volatile UCHAR * const)((_PCIOBASE + (_OFFSET))))
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#define _PCIOADDR(_OFFSET) ((_PCIOBASE + (_OFFSET)))
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//
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// The Physical IO Space for generation one machines starts at 0x8000_0000.
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// All IO external devices in either ISA space or PCI space live within
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// this domain. This also includes the on-board ethernet and scsi drivers,
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// the ISA bus interrupt controllers, display control.
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//
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//
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// PCI Configuration Space:
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//
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//
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// device cpu relative Address Config space address
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// ------ -------------------- ----------------
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//
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// 82378 ( SIO ) 0x8080_0800 - 0x8080_08ff 0x80_0800 - 0x80_08ff
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// scsi (79c974) 0x8080_1000 - 0x8080_10ff 0x80_1000 - 0x80_10ff
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// pci slot A 0x8080_2000 - 0x8080_20ff 0x80_2000 - 0x80_20ff
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// pci slot B 0x8080_4000 - 0x8080_40ff 0x80_4000 - 0x80_40ff
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// enet (79c974) 0x8080_8000 - 0x8080_80ff 0x80_8000 - 0x80_80ff
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#define RPciConfig(Slot,Offset) \
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(*(volatile ULONG * const)(_PCIOBASE + (HalpPciConfigSlot[Slot] + Offset)) )
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#define RPciVendor(Slot) \
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(*(volatile ULONG * const)(_PCIOBASE + (UCHAR)(HalpPciConfigSlot[Slot])) )
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#define RPciVendorId(Slot) \
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(*(volatile ULONG * const) (_PCIOBASE + (HalpPciConfigSlot[Slot])) )
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//(*(volatile ULONG * const) (_PCIOBASE + (0x800 << Slot) ) )
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//
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// I/O Device Addresses
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//
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// Device Registers IO Space Cpu Space
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// ---------------- -------- ---------
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//
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// Dma 1 registers, control 0x0000 - 0x000f 0x8000_0000 - _000f
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// 8259 interrupt 1 control 0x0020 0x8000_0020
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// 8259 interrupt 1 mask 0x0021 0x8000_0021
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#define MasterIntPort0 0x0020
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#define MasterIntPort1 0x0021
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//
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// AIP Primary xbus index 0x0022
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// AIP Primary Xbus target 0x0023
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// AIP Secondary Xbus
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// target 0x0024
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// AIP Secondary xbus
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// index 0x0025
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//
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#define AIP_PRIMARY_XBUS_INDEX 0x0022
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#define AIP_PRIMARY_XBUS_TARGET 0x0023
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#define AIP_SECONDARY_XBUS_INDEX 0x0024
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#define AIP_SECONDARY_XBUS_TARGET 0x0025
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// keyboard cs, Reset 0x0060
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// ( xbus irq 12 )
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// nmi status and control 0x0061
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// keyboard cs 0x0062
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// keyboard cs 0x0064
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// keyboard cs 0x0066
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/*
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** *******************************************
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**
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** Dallas 1385 Real Time Clock : System macros
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** dallas specific macros are in pxds1585.h
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*/
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// RTC address 0x0070
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// RTC read/writ 0x0071
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// NVRAM addr strobe 0 0x0072
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// NVRAM addr strobe 1 0x0075
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// NVRAM Read/Write 0x0077
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// RTC and NVRAM 0x0070 - 0077
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#define RTC_INDEX 0x0070 // index register
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#define RTC_DATA 0x0071 // data register
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#define NVRAM_ADDR0 0x0072 // address strobe 0
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#define NVRAM_ADDR1 0x0075 // address strobe 1
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#define NVRAM_RW 0x0077 // read write nvram?
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// Timer 0x0078 - 007f
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// DMA Page Registers 0x0080 - 0090
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// Port 92 Register 0x0080 - 0092
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// DMA Page Registers 0x0094 - 009f
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// 8259 interrupt 2 control 0x00A0 0x8000_00A0
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// 8259 interrupt 2 mask 0x00A1 0x8000_00A1
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#define SlaveIntPort0 0x00A0
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#define SlaveIntPort1 0x00A1
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// DMA 2 registers and
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// control 0x00c0 - 00df
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// AIP Configuration
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// Registers 0x026e - 026f
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// ( primary addr block )
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#define AIP_PRIMARY_CONFIG_INDEX_REG 0x026e
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#define AIP_PRIMARY_CNFG_DATA_REG 0x026f
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// Parallel Port 3 0x0278 - 027d
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// serial port2 0x02f8 - 02ff
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// secondary floppy
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// controller 0x0370 - 0377
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// parallel port 2 0x0378 - 037d
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// AIP Configuraiton Registers 0x0398 - 0399
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// ( secondary addr blck )
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#define AIP_SECOND_CONFIG_INDEX_REG 0x0398
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#define AIP_SECOND_CNFG_DATA_REG 0x0399
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// parallel port 1 0x03bc - 03bf
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// pcmcia config registers 0x03e0 - 03e3
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// primary floppy controller 0x03f0 - 03f7
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// serial port 1 0x03f8 - 03ff
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// dma 1 extended
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// mode regsiter 0x040b
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// dma scatter/gather
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// command status 0x0410 - 041f
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// dma scatter/gather
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// Dscrptr ( channel 0-3 ) 0x0420 - 042f
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// dma scatter/gather
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// Dscrptr ( channel 5-7 ) 0x0434 - 043f
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// dma high page registers 0x0481 - 0483
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// dma high page registers 0x0487
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// dma high page registers 0x0489
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// dma high page registers 0x048a - 048b
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// dma 2 extended mode
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// register 0x04d6
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// business audio control,
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// status, data registers 0x0830 - 0833
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// video asic registers 0x0840 - 0841
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#define DCC_INDEX 0x0840
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#define DCC_DATA 0x0841
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// bt445 ramdac registers 0x0860 - 086f
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#define BT445_ADDRESS 0x0860
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#define ADDRESS_REGISTER 0x0860 // same as the BT445_ADDR
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#define PRIMARY_PALETTE 0x0861 // Primary Color Palette address
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#define CHIP_CONTROL 0x0862 // function control register
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#define OVERLAY_PALETTE 0x0863 // Overlay Color Palette
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#define RGB_PIXEL_CONFIG 0x0865 // RGB configuration and control
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#define TIMING_PIXEL_CONFIG 0x0866 // pixel timing, configuration, control
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#define CURSOR_COLOR 0x0867 // cursor color
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// dram simm presence
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// detect register 0x0880
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// vram simm presence
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// detect register 0x0890
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// epxansion presence
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// detect register 0x08a0
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//
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//
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// Defines for Register Access:
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//
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#define rIndexRTC _IOREG( RTC_INDEX )
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#define rDataRTC _IOREG( RTC_DATA )
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#define rNvramData _IOREG( NVRAM_RW )
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#define rNvramAddr0 _IOREG( NVRAM_ADDR0 )
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#define rNvramAddr1 _IOREG( NVRAM_ADDR1 )
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#define rMasterIntPort0 _IOREG( MasterIntPort0 )
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#define rMasterIntPort1 _IOREG( MasterIntPort1 )
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#define rSlaveIntPort0 _IOREG( SlaveIntPort0 )
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#define rSlaveIntPort1 _IOREG( SlaveIntPort1 )
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#define rIndexAIP1 _IOREG( AIP_PRIMARY_XBUS_INDEX )
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#define rTargetAIP1 _IOREG( AIP_PRIMARY_XBUS_TARGET )
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#define rIndexAIP2 _IOREG( AIP_SECONDARY_XBUS_INDEX )
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#define rTargetAIP2 _IOREG( AIP_SECONDARY_XBUS_TARGET )
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#define rDccIndex _IOREG( DCC_INDEX )
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#define rDccData _IOREG( DCC_DATA )
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#define rRamDacAddr _IOREG( BT445_ADDRESS )
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#define rDacPrimeLut _IOREG( PRIMARY_PALETTE )
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#define rRamDacCntl _IOREG( CHIP_CONTROL )
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#define rDacOvlayLut _IOREG( OVERLAY_PALETTE )
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#define rDacPixelBit _IOREG( RGB_PIXEL_CONFIG )
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#define rDacPixelClks _IOREG( TIMING_PIXEL_CONFIG )
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#define rRamDacCursor _IOREG( CURSOR_COLOR )
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#endif
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