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422 lines
13 KiB
422 lines
13 KiB
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: fpreg.h $
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* $Revision: 1.19 $
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* $Date: 1996/05/14 02:32:57 $
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* $Locker: $
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*/
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#ifndef FPREG_H
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#define FPREG_H
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#define MAX_SYSTEM_CPU_NUM 2
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//
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// This file contains all of the definitions for the FirePower Control
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// registers. C code needing to access these registers should include this
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// file. If future boards differ from these definitions, we should move
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// the contents of this file into a board specific file, but still
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// have c code include fpreg.h
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//
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//
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// This is a variable that when set contains the virtual address of
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// where the system registers were mapped
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//
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extern PVOID HalpSystemRegisterBase;
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//
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// Code to write to a safe place (generate external bus cycle to work
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// around the TSC bug).
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//
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extern ULONG SafePlace;
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#define WriteSafePlace() \
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SafePlace = 0x0; \
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HalSweepDcacheRange(&SafePlace, 8);
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//
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// The following routine should be called whenever the order of writes
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// to a control register needs to be guaranteed.
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//
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#define FireSyncRegister() \
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__builtin_eieio() ;
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// __builtin_sync();
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//
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// After all writes to the Tsc registers, the system needs to
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// generate an off chip write request.
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//
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#define FireTscSyncRegister() \
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WriteSafePlace(); \
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KeFlushWriteBuffer();
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//
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// The following macro handles the conversion from BigEndian to LittleEndian
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// This is current setup as a compile time handling but could easily be'
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// made dynamic.
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//
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// Note: The following is the proper definition for Endianess but
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// it causes the Motorola Compiler to go nuts.
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//
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// #ifdef BIGENDIAN
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// #define _BE 1
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// #else
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// #define _BE 0
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// #endif
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//
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// #define _ENDIAN(_X) ((int)(_X) + (int)((_BE)?0:4))
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#ifdef BIGENDIAN
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#define _ENDIAN(_X) ((ULONG)_X + 0)
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#else
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// the NT is running in little endian mode.
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// The following conversion macro can be used only with
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// the addresses at double word boundary and in ASIC.
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// It is not required for the memory accesses.
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#define _ENDIAN(_X) ((ULONG)_X + 4)
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#endif
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//
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// These defines provide the mapping to turn an offset into
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// a pointer to the 32 bit register.
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//
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#define _SYSBASE ((PUCHAR)HalpSystemRegisterBase)
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#define _REG(_OFFSET) (*(volatile ULONG * const)(_ENDIAN(_SYSBASE + (_OFFSET))))
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#define _ADDR(_OFFSET) (_ENDIAN(_SYSBASE + (_OFFSET)))
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//
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// Register definitions with appropriate bit field defintions below.
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// Defines are used because not all of the compilers can be trusted
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// to treat bit field definitions correctly for this architecture.
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//
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#define rInterruptRequest _REG( 0x000000 )
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#define rInterruptRequestSet _REG( 0x000008 )
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#define rInterruptMask0 _REG( 0x000100 )
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#define rInterruptMask1 _REG( 0x000108 )
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#define rInterruptMask2 _REG( 0x000110 )
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#define rInterruptMask3 _REG( 0x000118 )
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#define rInterruptPending0 _REG( 0x000200 )
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#define rInterruptPending1 _REG( 0x000208 )
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#define rInterruptPending2 _REG( 0x000210 )
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#define rInterruptPending3 _REG( 0x000218 )
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#define rCPUMessageInterrupt _REG( 0x000300 )
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#define rCPUMessageInterruptSet _REG( 0x000308 )
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#define rPCIBusErrorCause _REG( 0x000400 )
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#define rPCIBusErrorCauseSet _REG( 0x000408 )
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#define rPCIBusErrorAddressRegister _REG( 0x000410 )
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#define rCPUBusErrorCause _REG( 0x000800 )
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#define rCPUBusErrorCauseSet _REG( 0x000808 )
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#define rCPUBusErrorAddressRegister _REG( 0x000810 )
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#define rErrorStatus0 _REG( 0x001000 )
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#define rErrorStatus0Set _REG( 0x001008 )
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#define rErrorMask _REG( 0x001010 )
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#define rErrorAddr0 _REG( 0x001120 )
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#define rErrorAddr1 _REG( 0x001128 )
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#define rErrorAddr2 _REG( 0x001130 )
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#define rErrorAddr3 _REG( 0x001138 )
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#define rVidInt _REG( 0x001140 )
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#define rVidIntSet _REG( 0x001148 )
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#define rVidIntMask _REG( 0x001150 )
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#define rTscControl _REG( 0x100000 )
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#define rFbControl _REG( 0x100008 )
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#define rEsccControl _REG( 0x100010 )
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#define rEsccL2FLush _REG( 0x100018 )
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#define rScratchPad0 _REG( 0x100020 )
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#define rScratchPad1 _REG( 0x100028 )
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#define rScratchPad2 _REG( 0x100030 )
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#define rLowPowerControl _REG( 0x100080 )
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#define rRomControl _REG( 0x100100 )
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#define rTscStatus0 _REG( 0x100200 )
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#define rTscRevision _REG( 0x100300 )
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#define rMemBank0Config _REG( 0x100400 )
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#define rMemBank1Config _REG( 0x100408 )
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#define rMemBank2Config _REG( 0x100410 )
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#define rMemBank3Config _REG( 0x100418 )
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#define rMemBank4Config _REG( 0x100420 )
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#define rMemBank5Config _REG( 0x100428 )
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#define rMemBank6Config _REG( 0x100430 )
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#define rMemBank7Config _REG( 0x100438 )
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#define rMemDramTiming _REG( 0x100500 )
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#define rMemVramTiming _REG( 0x100508 )
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#define rMemRefresh _REG( 0x100510 )
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#define rVidControl _REG( 0x100518 )
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#define rVidPixelsPerLineLo _REG( 0x100520 )
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#define rVidPixelsPerLineHi _REG( 0x100528 )
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#define rIOControl _REG( 0x101000 )
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#define rPCIConfigType _REG( 0x101100 )
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#define rPIOPendingCount _REG( 0x101200 )
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#define rDMAPendingCount _REG( 0x101300 )
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#define rPCIVendorID _REG( 0x400100 )
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#define rPCIDeviceID _REG( 0x400108 )
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#define rPCICommand _REG( 0x400110 )
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#define rPCIStatus _REG( 0x400118 )
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#define rPCIRevisionID _REG( 0x400120 )
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#define rPCIClassCode _REG( 0x400128 )
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#define rPCIHeaderType _REG( 0x400140 )
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//
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// Addrs non-dereferenced register declarations
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//
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#define rInterruptMask _ADDR(0x000100)
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#define rInterruptPending _ADDR(0x000200)
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//#define memCpuMailBox _ENDIAN(0x80002F80)
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#define memCpuMailBox 0x80002F80
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//
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// Use the value of the last defines register
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//
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#define NBPG 4096
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#define roundup(_X, _Y) (((_X) + ((_Y)-1)) / (_Y))
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#define btorp(_X) (roundup((_X), NBPG) )
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#define REGISTER_PAGES (btorp(0x400140))
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//
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// Place Macros/Masks/Bit Definitions in this area for each of the
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// control registers.
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//
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// rInterruptRequest
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// rInterruptRequestSet
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// rInterruptMask0
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// rInterruptMask1
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// rInterruptMask2
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// rInterruptMask3
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#define RInterruptMask(_CPU) \
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(*(volatile ULONG * const)(rInterruptMask + (ULONG)((_CPU) << 3)))
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//(*(volatile ULONG * const)(rInterruptMask + ((_CPU) * 8)))
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#define RInterruptPending(_CPU) \
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(*(volatile ULONG * const)(rInterruptPending + ((_CPU) * 8)))
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//
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// To guarantee that the Mask write is complete we must insure that:
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// a) the ordering does not change and b) the all pending reads are
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// complete before we continue. Since we are reading the address
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// we write, the processor will not re-order the read/write. We
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// must use a "sync" to guarantee that the EE bit is not set
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// until after the data from the read of RInterruptMask returns.
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//
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#define WaitForRInterruptMask(_CPU) \
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{ \
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volatile ULONG dummyVar; \
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FireSyncRegister(); \
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dummyVar = RInterruptMask(_CPU);\
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__builtin_sync(); \
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}
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#define MemSetCpuAddr(_CPU) \
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(*(volatile ULONG * const)( memCpuMailBox + ( (( _CPU ) * 8 ) + 0x4 )))
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#define MemStartCpu(_CPU) \
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(*(volatile ULONG * const)( memCpuMailBox + (( _CPU ) * 8 )))
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#define ALL_INTS_OFF 0x00000000
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#define ALL_INTS_ON 0xffffffff
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#define CPU_MESSAGE_NUM 31
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#define MEMORY_ERROR_VIDEO_NUM 30
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#define PCI_ERROR_NUM 29
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#define CPU_BUS_ERROR_NUM 28
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#define SIO_NMI_NUM 27
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#define LX_PCI_SLOT_0_NUM 26
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#define LX_PCI_SLOT_1_NUM 25
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#define LX_PCI_SLOT_2_NUM 24
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#define LX_PCI_SLOT_3_NUM 23
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#define LX_PCI_IDE_INTA_NUM 22
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#define LX_PCI_IDE_INTB_NUM 21
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#define ENET_NUM 26
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#define SCSI_NUM 25
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#define PCI_SLOT_1_NUM 23
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#define PCI_SLOT_0_NUM 22
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#define SOFTWARE0_NUM 19
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#define SOFTWARE1_NUM 18
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#define SOFTWARE2_NUM 17
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#define SOFTWARE3_NUM 16
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#define ISA_PIND06_NUM 15
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#define ISA_PIND07_NUM 14
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#define MOUSE_NUM 12
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#define ISA_PIND04_NUM 11
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#define AUDIO_NUM 10
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#define ISA_PINB04_NUM 9
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#define RTC_NUM 8
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#define PARALLEL_NUM 7
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#define FLOPPY_NUM 6
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#define DISPLAY_NUM 5
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#define SERIAL1_NUM 4
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#define SERIAL2_NUM 3
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#define KEYBOARD_NUM 1
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#define TIMER_NUM 0
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#define NUM_2_INT(x) (1 << x )
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#define CPU_MESSAGE_INT NUM_2_INT( CPU_MESSAGE_NUM )
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#define MEMORY_ERROR_VIDEO_INT NUM_2_INT( MEMORY_ERROR_VIDEO_NUM )
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#define PCI_ERROR_INT NUM_2_INT( PCI_ERROR_NUM )
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#define CPU_BUS_ERROR_INT NUM_2_INT( CPU_BUS_ERROR_NUM )
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#define SIO_NMI_INT NUM_2_INT( SIO_NMI_NUM )
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#define LX_PCI_SLOT_0_INT NUM_2_INT( LX_PCI_SLOT_0_NUM )
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#define LX_PCI_SLOT_1_INT NUM_2_INT( LX_PCI_SLOT_1_NUM )
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#define LX_PCI_SLOT_2_INT NUM_2_INT( LX_PCI_SLOT_2_NUM )
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#define LX_PCI_SLOT_3_INT NUM_2_INT( LX_PCI_SLOT_3_NUM )
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#define LX_PCI_IDE_INTA_INT NUM_2_INT( LX_PCI_IDE_INTA_NUM )
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#define LX_PCI_IDE_INTB_INT NUM_2_INT( LX_PCI_IDE_INTB_NUM )
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#define ENET_INT NUM_2_INT( ENET_NUM )
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#define SCSI_INT NUM_2_INT( SCSI_NUM )
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#define PCI_SLOT_1_INT NUM_2_INT( PCI_SLOT_1_NUM )
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#define PCI_SLOT_0_INT NUM_2_INT( PCI_SLOT_0_NUM )
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#define SOFTWARE0_INT NUM_2_INT( SOFTWARE0_NUM )
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#define SOFTWARE1_INT NUM_2_INT( SOFTWARE1_NUM )
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#define SOFTWARE2_INT NUM_2_INT( SOFTWARE2_NUM )
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#define SOFTWARE3_INT NUM_2_INT( SOFTWARE3_NUM )
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#define ISA_PIND06_INT NUM_2_INT( ISA_PIND06_NUM )
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#define ISA_PIND07_INT NUM_2_INT( ISA_PIND07_NUM )
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#define MOUSE_INT NUM_2_INT( MOUSE_NUM )
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#define ISA_PIND04_INT NUM_2_INT( ISA_PIND04_NUM )
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#define AUDIO_INT NUM_2_INT( AUDIO_NUM )
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#define ISA_PINB04_INT NUM_2_INT( ISA_PINB04_NUM )
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#define RTC_INT NUM_2_INT( RTC_NUM )
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#define PARALLEL_INT NUM_2_INT( PARALLEL_NUM )
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#define FLOPPY_INT NUM_2_INT( FLOPPY_NUM )
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#define DISPLAY_INT NUM_2_INT( DISPLAY_NUM )
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#define SERIAL1_INT NUM_2_INT( SERIAL1_NUM )
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#define SERIAL2_INT NUM_2_INT( SERIAL2_NUM )
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#define KEYBOARD_INT NUM_2_INT( KEYBOARD_NUM )
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#define TIMER_INT NUM_2_INT( TIMER_NUM )
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#define ALL_BITS_CLEAR 0xffffffff
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#define ENABLE_EISA_MASK 0x0000ffff
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#define SET_INTS_CLEAR 0xffffffff
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#define EISA_INTS_ON 0xffff0000
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#define SCSI_EISA_INT 0x00002000
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// rInterruptPending0
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// rInterruptPending1
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// rInterruptPending2
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// rInterruptPending3
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// rCPUMessageInterrupt
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// rCPUMessageInterruptSet
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// rPCIBusErrorCause
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// rPCIBusErrorCauseSet
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#define PCI_ERROR_SIGNALED_SYS 0x00000001
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#define PCI_ERROR_DATA_PARITY 0x00000002
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#define PCI_ERROR_DEV_TIMEOUT 0x00000004
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#define PCI_ERROR_TARGET_ABORT 0x00000008
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// rPCIBusErrorAddressRegister
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// rCPUBusErrorCause
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#define CPU_ERROR_ILLEGAL_SAACC 0x00000001
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#define CPU_ERROR_ADDR_PARITY 0x00000002
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#define CPU_ERROR_DISCONTIG_ISA 0x00000004
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// rCPUBusErrorCauseSet
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// rCPUBusErrorAddressRegister
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// rErrorStatus0
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#define ERROR_ECC_CORRECTED 0x02000000
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#define ERROR_ECC_FAILED 0x04000000
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#define ERROR_ADDR_PARITY 0x08000000
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#define ERROR_DATA_PARITY 0x10000000
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#define ERROR_MEM_PARITY 0x20000000
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#define ERROR_INVALID_XACT 0x40000000
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// rErrorStatus0Set
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// rErrorMask
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#define ECC_CORRECTED 0x02000000
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#define ECC_FAILED 0x04000000
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#define ADDRESS_PARITY_ERROR 0x08000000
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#define DATA_PARITY_ERROR 0x10000000
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#define MEM_PARITY_ERROR 0x20000000
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#define INVALID_XACT 0x40000000
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// rErrorAddr0
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// rErrorAddr1
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// rErrorAddr2
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// rErrorAddr3
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// rVidInt
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// rVidIntSet
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// rVidIntMask
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// rTscControl
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#define L2_PRESENT 0x01000000
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#define MP_CONFIG 0x04000000
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#define ECC_ENABLE 0x08000000
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#define LITTLE_ENDIAN 0x10000000
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#define BRIDGE_MODE 0x20000000
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// rFbControl
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#define CPU_VRAM_SWAP_BYTES 0x01000000
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#define CPU_VRAM_ADDR_MUNGE 0x02000000
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#define CPU_INVERT_FB_ADDR_LSB 0x04000000
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#define PCI_VRAM_SWAP_BYTES 0x08000000
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#define PCI_VRAM_SWAP_ENABLES 0x10000000
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#define PCI_INVERT_FB_ADDR2 0x20000000
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// rEsccControl
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// rEsccL2FLush
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// rScratchPad0
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// rScratchPad1
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// rScratchPad2
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// rLowPowerControl
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// rRomControl
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// rTscStatus0
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#define ROM_BUSY 0x00000001
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#define WRQ_FULL 0x00000002
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#define I2Q_FULL 0x00000004
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#define WRQ_EMPTY 0x00000008
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#define I2Q_EMPTY 0x00000010
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//#define CPU_MASK 0x000000c0
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#define CPU_MASK 0xc0000000
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#define GetCpuId() ((rTscStatus0 & CPU_MASK) >> 30)
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// rTscRevision
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// rMemBank0Config
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// rMemBank1Config
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// rMemBank2Config
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// rMemBank3Config
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// rMemBank4Config
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// rMemBank5Config
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// rMemBank6Config
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// rMemBank7Config
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// rMemDramTiming
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// rMemVramTiming
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// rMemRefresh
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// rVidControl
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// rVidPixelsPerLineLo
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// rVidPixelsPerLineHi
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// rIOControl
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// rPCIConfigType
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#define PCI_TYPE1_CYCLE 0x00000001
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// rPIOPendingCount
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#define PENDING_COUNTMASK 0x0000007f
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#define PCI_BRIDGE_MODE 0x00000080
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// rDMAPendingCount
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// rPCIVendorID
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// rPCIDeviceID
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// rPCICommand
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// rPCIStatus
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#define PCI_DATA_PARITY_ERROR 0x00008000
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#define PCI_SIGNLD_SYSTEM_ERR 0x00004000
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#define PCI_RCVD_MASTER_ABORT 0x00002000
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#define PCI_RCVD_TARGET_ABORT 0x00001000
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#define PCI_SGNLD_TARGET_ABORT 0x00000800
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#define PCI_DATA_PARITY_DETECT 0x00000100
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// rPCIRevisionID
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// rPCIClassCode
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// rPCIHeaderType
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#endif // FPREG_H
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