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1105 lines
28 KiB
1105 lines
28 KiB
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: pxcache.s $
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* $Revision: 1.12 $
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* $Date: 1996/03/05 02:16:01 $
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* $Locker: $
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*/
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//++
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//
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// Copyright (c) 1993, 1994, 1995 IBM Corporation
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//
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// Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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// contains copyrighted material. Use of this file is restricted
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// by the provisions of a Motorola Software License Agreement.
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//
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// Module Name:
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//
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// pxcache.s
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//
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// Abstract:
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//
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// This module implements the routines to flush cache on the PowerPC.
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//
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// Author:
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//
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// Peter L. Johnston ([email protected]) September 1993
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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// 27-Dec-93 plj Added 603 support.
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// 13-Mar-94 plj Fixed problem introduced during switch to pas,
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// added 604 support.
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// 18-Jan-95 plj Add 603+, 604+ and 620 support.
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//
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//--
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#include "kxppc.h"
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.set HID0, 1008 // H/W Implementation Dependent reg 0
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//
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// Define various known processor types.
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//
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.set PV601, 1 // 601
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.set PV603, 3 // 603
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.set PV603P, 6 // 603 plus
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.set PV604, 4 // 604
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.set PV604P, 9 // 604 plus
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.set PV620, 20 // 620
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//
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// Note, in the following, the 603's "I-Cache Flash Invalidate"
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// and the 604's "I-Cache Invalidate All" basically perform the
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// same function although the usage is slightly different.
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// In the 603 case, ICFI must be cleared under program control
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// after it is set. In the 604 the bit clears automatically.
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// The 620's ICEFI behaves in the same way as the 604's ICIA.
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//
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.set H0_603_ICFI, 0x0800 // I-Cache Flash Invalidate
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.set H0_604_ICIA, 0x0800 // I-Cache Invalidate All
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.set H0_620_ICEFI,0x0800 // I-Cache Edge Flash Invalidate
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//
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// Cache layout
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//
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// Processor | Size (bytes) | Line Size | Block Size | PVR Processor
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// | I-Cache | D-Cache | | | Version
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// ----------------------------------------------------------------------
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// 601 | 32KB Unified | 64 bytes | 32 bytes | 0x0001xxxx
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// 603 | 8KB | 8KB | 32 | 32 | 0x0003xxxx
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// 603+ | 16KB | 16KB | 32 | 32 | 0x0006xxxx
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// 604 | 16KB | 16KB | 32 | 32 | 0x0004xxxx
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// 604+ | 32KB | 32KB | 32 | 32 | 0x0009xxxx
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// 620 | 32KB | 32KB | 64 | 64 | 0x0014xxxx
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//
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.set DCLSZ601, 64 // 601 cache line size
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.set DCBSZ601, 32 // 601 cache block size
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.set DCL601, 32 * 1024 / DCLSZ601 // 601 num cache lines
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.set DCBSZL2601, 5 // 601 log2(block size)
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.set DCBSZ603, 32 // 603 cache block size
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.set DCB603, 8 * 1024 / DCBSZ603 // 603 num cache blocks
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.set DCBSZL2603, 5 // 603 log2(block size)
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.set DCB603P, 16 * 1024 / DCBSZ603 // 603+ num cache blocks
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.set DCBSZ604, 32 // 604 cache block size
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.set DCB604, 16 * 1024 / DCBSZ604 // 604 num cache blocks
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.set DCBSZL2604, 5 // 604 log2(block size)
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.set DCB604P, 32 * 1024 / DCBSZ604 // 604+ num cache blocks
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.set DCBSZ620, 64 // 620 cache block size
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.set DCB620, 32 * 1024 / DCBSZ620 // 620 num cache blocks
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.set DCBSZL2620, 6 // 620 log2(block size)
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//
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// The following variables are declared locally so their addresses
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// will appear in the TOC. During initialization, we overwrite
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// the TOC entries with the entry points for the cache flushing
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// routines appropriate for the processor we are running on.
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//
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// It is done this way rather than filling in a table to reduce the
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// number of access required to get the address at runtime.
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// (This is known as "Data in TOC" which is not very much used in
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// NT at this time).
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//
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.data
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.globl HalpSweepDcache
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HalpSweepDcache: .long 0
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.globl HalpSweepIcache
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HalpSweepIcache: .long 0
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.globl HalpSweepDcacheRange
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HalpSweepDcacheRange: .long 0
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.globl HalpSweepIcacheRange
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HalpSweepIcacheRange: .long 0
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//++
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//
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// Routine Description:
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//
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// HalpCacheSweepSetup
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//
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// This routine is called during HAL initialization. Its function
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// is to set the branch tables for cache flushing routines according
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// to the processor type.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpCacheSweepSetup)
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mfpvr r.3 // get processor type
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rlwinm r.3, r.3, 16, 0xffff // remove version
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cmpwi r.3, PV603P // binary search for the right code
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lwz r.4, [toc].data(r.toc) // get address of local data section
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bge hcss.high // jif 603+ or greater
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cmpwi r.3, PV603
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beq hcss.603 // jif 603
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bgt hcss.604 // > 603, < 603+ must be 604
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//
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// processor is a 601
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//
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lwz r.5, [toc]HalpSweepDcache601(r.toc)
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lwz r.7, [toc]HalpSweepDcacheRange601(r.toc)
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lwz r.8, [toc]HalpSweepIcacheRange601(r.toc)
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mr r.6, r.5 // 601 icache use dcache routine
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b hcss.done
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//
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// processor is a 603
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//
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hcss.603:
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lwz r.5, [toc]HalpSweepDcache603(r.toc)
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lwz r.6, [toc]HalpSweepIcache603(r.toc)
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lwz r.7, [toc]HalpSweepDcacheRange603(r.toc)
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lwz r.8, [toc]HalpSweepIcacheRange603(r.toc)
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b hcss.done
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//
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// processor is a 604
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//
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hcss.604:
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lwz r.5, [toc]HalpSweepDcache604(r.toc)
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lwz r.6, [toc]HalpSweepIcache604(r.toc)
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lwz r.7, [toc]HalpSweepDcacheRange604(r.toc)
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lwz r.8, [toc]HalpSweepIcacheRange604(r.toc)
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b hcss.done
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//
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// Processor type >= 603+, continue isolation of processor type.
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//
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hcss.high:
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beq hcss.603p // jif 603 plus
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cmpwi cr.0, r.3, PV604P
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cmpwi cr.1, r.3, PV620
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beq cr.0, hcss.604p // jif 604 plus
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beq cr.1, hcss.620 // jif 620
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//
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// If we got here we are running on a processor whose cache characteristics
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// are not known. Return non-zero for error.
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//
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li r.3, 1
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blr
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//
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// processor is a 603 plus
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//
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hcss.603p:
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lwz r.5, [toc]HalpSweepDcache603p(r.toc)
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lwz r.6, [toc]HalpSweepIcache603p(r.toc)
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lwz r.7, [toc]HalpSweepDcacheRange603p(r.toc)
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lwz r.8, [toc]HalpSweepIcacheRange603p(r.toc)
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b hcss.done
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//
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// processor is a 604 plus
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//
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hcss.604p:
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lwz r.5, [toc]HalpSweepDcache604p(r.toc)
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lwz r.6, [toc]HalpSweepIcache604p(r.toc)
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lwz r.7, [toc]HalpSweepDcacheRange604p(r.toc)
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lwz r.8, [toc]HalpSweepIcacheRange604p(r.toc)
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b hcss.done
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//
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// processor is a 620
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//
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hcss.620:
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lwz r.5, [toc]HalpSweepDcache620(r.toc)
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lwz r.6, [toc]HalpSweepIcache620(r.toc)
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lwz r.7, [toc]HalpSweepDcacheRange620(r.toc)
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lwz r.8, [toc]HalpSweepIcacheRange620(r.toc)
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b hcss.done
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hcss.done:
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//
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// r.5 thru r.9 contain the address of the function descriptors
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// for the routines we really want to use. Dereference them to
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// get at the entry point addresses.
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//
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lwz r.5, 0(r.5)
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lwz r.6, 0(r.6)
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lwz r.7, 0(r.7)
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lwz r.8, 0(r.8)
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//
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// Store the entry point addresses directly into the TOC.
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// This is so direct linkage from within the HAL to the
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// generic cache flushing routines can get to the desired
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// routines for this processor.
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//
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stw r.5, [toc]HalpSweepDcache(r.toc)
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stw r.6, [toc]HalpSweepIcache(r.toc)
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stw r.7, [toc]HalpSweepDcacheRange(r.toc)
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stw r.8, [toc]HalpSweepIcacheRange(r.toc)
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//
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// Modify the Function Descriptors for the generic routines to
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// point directly at the target routines so that linkage from
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// other executables (eg the kernel) will be direct rather
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// than via the generic routines.
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//
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lwz r.3, [toc]HalSweepDcache(r.toc)
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lwz r.4, [toc]HalSweepIcache(r.toc)
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stw r.5, 0(r.3)
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stw r.6, 0(r.4)
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lwz r.3, [toc]HalSweepDcacheRange(r.toc)
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lwz r.4, [toc]HalSweepIcacheRange(r.toc)
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stw r.7, 0(r.3)
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stw r.8, 0(r.4)
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li r.3, 0 // return code = success
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LEAF_EXIT(HalpCacheSweepSetup)
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//++
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//
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// Routines HalSweepDcache
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// HalSweepIcache
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// HalSweepDcacheRange
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// HalSweepIcacheRange
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//
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// are simply dispatch points for the appropriate routine for
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// the processor being used.
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//
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//--
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LEAF_ENTRY(HalSweepDcache)
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lwz r.12, [toc]HalpSweepDcache(r.toc)
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mtctr r.12
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bctr
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DUMMY_EXIT(HalSweepDcache)
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LEAF_ENTRY(HalSweepIcache)
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lwz r.12, [toc]HalpSweepIcache(r.toc)
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mtctr r.12
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bctr
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DUMMY_EXIT(HalSweepIcache)
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LEAF_ENTRY(HalSweepDcacheRange)
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lwz r.12, [toc]HalpSweepDcacheRange(r.toc)
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mtctr r.12
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bctr
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DUMMY_EXIT(HalSweepDcacheRange)
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LEAF_ENTRY(HalSweepIcacheRange)
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lwz r.12, [toc]HalpSweepIcacheRange(r.toc)
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mtctr r.12
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bctr
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DUMMY_EXIT(HalSweepIcacheRange)
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//++
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//
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// 601 Cache Flushing Routines
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//
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// The 601 has a unified instruction/data cache. For this reason
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// we need only two routines, one to sweep the entire cache and
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// another to sweep a given range.
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//
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//
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//
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//
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// HalpSweepDcache601
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//
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// Sweep the entire instruction/data cache. This is accomplished
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// by loading the cache with data corresponding to a known address
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// range and then ensuring that each block in the cache is not dirty.
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//
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// Note that the 601 line size is 64 bytes and its block size is 32
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// bytes. When we load any byte within a line, both blocks in that
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// line are loaded into the cache (if not already present). We must
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// clean each block individually.
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//
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// In an effort to maximize the possibilities that (a) the addressed
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// data is already in the cache and (b) there is some use in having
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// this data in the cache, we use the lower end of the hashed page
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// table as the data to be loaded and we use dcbst rather than dcbf
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// to force the block to memory (and leave it valid in the cache as
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// well).
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpSweepDcache601)
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mfsdr1 r.3 // fill the D cache from memory
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// allocated to the hashed page
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// table (it's something useful).
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li r.4, DCL601 // size of cache in cache lines
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mtctr r.4
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DISABLE_INTERRUPTS(r.10,r.11)
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sync
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oris r.3, r.3, 0x8000 // get VA of hashed page table
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subi r.5, r.3, DCBSZ601 // dec addr prior to inc
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hsd601.ld:
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lbzu r.8, DCLSZ601(r.5)
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bdnz hsd601.ld
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ENABLE_INTERRUPTS(r.10)
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LEAF_EXIT(HalpSweepDcache601)
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//++
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//
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// HalpSweepDcacheRange601
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//
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// HalpSweepDcacheRange603
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//
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// HalpSweepDcacheRange603p
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//
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// HalpSweepDcacheRange604
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//
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// HalpSweepDcacheRange604p
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//
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// Force data in a given address range to memory.
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//
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// Because this routine works on a range of blocks and block size
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// is the same on 601, 603, 603+, 604 and 604+ we can use the same
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// code for each of them.
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//
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// Arguments:
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//
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// r.3 Start address
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// r.4 Length (in bytes)
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpSweepDcacheRange601)
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ALTERNATE_ENTRY(HalpSweepDcacheRange603)
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ALTERNATE_ENTRY(HalpSweepDcacheRange603p)
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ALTERNATE_ENTRY(HalpSweepDcacheRange604)
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ALTERNATE_ENTRY(HalpSweepDcacheRange604p)
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rlwinm r.5, r.3, 0, DCBSZ601-1 // isolate offset in start block
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addi r.4, r.4, DCBSZ601-1 // bump range by block sz - 1
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add r.4, r.4, r.5 // add start block offset
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srwi r.4, r.4, DCBSZL2601 // number of blocks
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mtctr r.4
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sync
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hsdr601.fl:
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dcbst 0, r.3 // flush block
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addi r.3, r.3, DCBSZ601 // bump address
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bdnz hsdr601.fl
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LEAF_EXIT(HalpSweepDcacheRange601)
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//++
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//
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// HalpSweepIcacheRange601
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//
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// Due to the unified cache, this routine is meaningless on a 601.
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// The reason for flushing a range of instruction address is because
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// of code modification (eg breakpoints) in which case the nature
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// of the unified cache is that the *right* code is in the cache,
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// or because of a transfer of a code page in which case the unified
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// snooping cache will have done the right thing.
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//
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// Therefore this routine simply returns.
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//
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// Arguments:
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//
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// r.3 Start address
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// r.4 Length (in bytes)
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpSweepIcacheRange601)
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// return
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LEAF_EXIT(HalpSweepIcacheRange601)
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//++
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//
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// 603, 603+ Cache Flushing Routines
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//
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// The 603 has seperate instruction and data caches of 8 KB each.
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|
// The 603+ has seperate instruction and data caches of 16 KB each.
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// Line size = Block size = 32 bytes.
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//
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// The mechanics of cache manipulation are the same for the 603 and
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// 603+.
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//
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//
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//
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// HalpSweepDcache603 HalpSweepDcache603p
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//
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// Sweep the entire data cache. This is accomplished by loading
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// the cache with data corresponding to a known address range and
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|
// then ensuring that each block in the cache is not dirty.
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//
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|
// The 603 does not have a hashed page table so we can't use the
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// hashed page table as the data range. Instead use the start of
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// KSEG0.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpSweepDcache603p)
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li r.4, DCB603P // size of 603+ cache in blocks
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b hsd603
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DUMMY_EXIT(HalpSweepDcache603p)
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|
|
LEAF_ENTRY(HalpSweepDcache603)
|
|
|
|
li r.4, DCB603 // size of 603 cache in blocks
|
|
hsd603:
|
|
mtctr r.4
|
|
DISABLE_INTERRUPTS(r.10,r.11)
|
|
sync // ensure ALL previous stores completed
|
|
LWI(r.3,0x80000000) // known usable virtual address
|
|
subi r.5, r.3, DCBSZ603 // dec addr prior to inc
|
|
hsd603.ld:
|
|
lbzu r.8, DCBSZ603(r.5)
|
|
bdnz hsd603.ld
|
|
ENABLE_INTERRUPTS(r.10)
|
|
|
|
mtctr r.4
|
|
hsd603.fl:
|
|
dcbst 0, r.3 // ensure block is in memory
|
|
addi r.3, r.3, DCBSZ603 // bump address
|
|
bdnz hsd603.fl
|
|
|
|
LEAF_EXIT(HalpSweepDcache603)
|
|
|
|
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepIcache603 HalpSweepIcache603p
|
|
//
|
|
// Sweep the entire instruction cache. The instruction cache (by
|
|
// definition) can never contain modified code (hence there are no
|
|
// icbf or icbst instructions). Therefore what we really need to do
|
|
// here is simply invalidate every block in the cache. This can be
|
|
// done by toggling the Instruction Cache Flash Invalidate (ICFI) bit
|
|
// in the 603's HID0 register.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalpSweepIcache603)
|
|
|
|
ALTERNATE_ENTRY(HalpSweepIcache603p)
|
|
|
|
mfspr r.3, HID0 // 603, use Instruction
|
|
ori r.4, r.3, H0_603_ICFI // Cache Flash Invalidate
|
|
|
|
isync
|
|
mtspr HID0, r.4 // invalidate I-Cache
|
|
mtspr HID0, r.3 // re-enable
|
|
|
|
LEAF_EXIT(HalpSweepIcache603)
|
|
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepIcacheRange603 HalpSweepIcacheRange603p
|
|
//
|
|
// Remove a range of instructions from the instruction cache.
|
|
//
|
|
// Note that if this is going to take a long time we flash
|
|
// invalidate the I cache instead. Currently I define a
|
|
// "long time" as greater than 4096 bytes which amounts to
|
|
// 128 trips thru this loop (which should run in 256 clocks).
|
|
// This number was selected without bias or forethought from
|
|
// thin air - plj. I chose this number because gut feel tells
|
|
// me that it will cost me more than 256 clocks in cache misses
|
|
// trying to get back to the function that requested the cache
|
|
// flush in the first place.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// r.3 Start address
|
|
// r.4 Length (in bytes)
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalpSweepIcacheRange603)
|
|
|
|
ALTERNATE_ENTRY(HalpSweepIcacheRange603p)
|
|
|
|
cmpwi r.4, 4096 // if range > 4096 bytes, flush
|
|
bgt- ..HalpSweepIcache603 // entire I cache
|
|
|
|
rlwinm r.5, r.3, 0, DCBSZ603-1 // isolate offset in start block
|
|
addi r.4, r.4, DCBSZ603-1 // bump range by block sz - 1
|
|
add r.4, r.4, r.5 // add start block offset
|
|
srwi r.4, r.4, DCBSZL2603 // number of blocks
|
|
mtctr r.4
|
|
hsir603.fl:
|
|
icbi 0, r.3 // invalidate block in I cache
|
|
addi r.3, r.3, DCBSZ603 // bump address
|
|
bdnz hsir603.fl
|
|
|
|
LEAF_EXIT(HalpSweepIcacheRange603)
|
|
|
|
|
|
//++
|
|
//
|
|
// 604 Cache Flushing Routines
|
|
//
|
|
// The 604 has seperate instruction and data caches of 16 KB each.
|
|
// The 604+ has seperate instruction and data caches of 32 KB each.
|
|
// Line size = Block size = 32 bytes.
|
|
//
|
|
//
|
|
//
|
|
// HalpSweepDcache604 HalpSweepDcache604p
|
|
//
|
|
// Sweep the entire data cache. This is accomplished by loading
|
|
// the cache with data corresponding to a known address range and
|
|
// then ensuring that each block in the cache is not dirty.
|
|
//
|
|
// As in the 601 case, we use the Hashed Page Table for the data
|
|
// in an effort to minimize performance lost by force feeding the
|
|
// cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
|
|
LEAF_ENTRY(HalpSweepDcache604p)
|
|
|
|
li r.4, DCB604P // size of 604+ cache in blocks
|
|
b hsd604
|
|
|
|
DUMMY_EXIT(HalpSweepDcache604p)
|
|
|
|
|
|
|
|
LEAF_ENTRY(HalpSweepDcache604)
|
|
|
|
li r.4, DCB604 // size of cache in cache blocks
|
|
hsd604:
|
|
mfsdr1 r.3 // fill the D cache from memory
|
|
// allocated to the hashed page
|
|
// table (it's something useful).
|
|
mtctr r.4
|
|
DISABLE_INTERRUPTS(r.10,r.11)
|
|
sync // ensure ALL previous stores completed
|
|
oris r.3, r.3, 0x8000 // get VA of hashed page table
|
|
subi r.5, r.3, DCBSZ604 // dec addr prior to inc
|
|
hsd604.ld:
|
|
lbzu r.8, DCBSZ604(r.5)
|
|
bdnz hsd604.ld
|
|
ENABLE_INTERRUPTS(r.10)
|
|
|
|
LEAF_EXIT(HalpSweepDcache604)
|
|
|
|
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepIcache604 HalpSweepIcache604p
|
|
//
|
|
// Sweep the entire instruction cache. This routine is functionally
|
|
// similar to the 603 version except that on the 604 the bit in HID0
|
|
// (coincidentally the *same* bit) is called Instruction Cache Invali-
|
|
// sate All (ICIA) and it clears automatically after being set.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalpSweepIcache604)
|
|
|
|
ALTERNATE_ENTRY(HalpSweepIcache604p)
|
|
|
|
mfspr r.3, HID0 // 604, use Instruction
|
|
ori r.3, r.3, H0_604_ICIA // Cache Invalidate All
|
|
isync
|
|
mtspr HID0, r.3 // invalidate I-Cache
|
|
|
|
LEAF_EXIT(HalpSweepIcache604)
|
|
|
|
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepIcacheRange604 HalpSweepIcacheRange604p
|
|
//
|
|
// Remove a range of instructions from the instruction cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// r.3 Start address
|
|
// r.4 Length (in bytes)
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalpSweepIcacheRange604)
|
|
|
|
ALTERNATE_ENTRY(HalpSweepIcacheRange604p)
|
|
|
|
rlwinm r.5, r.3, 0, DCBSZ604-1 // isolate offset in start block
|
|
addi r.4, r.4, DCBSZ604-1 // bump range by block sz - 1
|
|
add r.4, r.4, r.5 // add start block offset
|
|
srwi r.4, r.4, DCBSZL2604 // number of blocks
|
|
mtctr r.4
|
|
hsir604.fl:
|
|
icbi 0, r.3 // invalidate block in I cache
|
|
addi r.3, r.3, DCBSZ604 // bump address
|
|
bdnz hsir604.fl
|
|
|
|
LEAF_EXIT(HalpSweepIcacheRange604)
|
|
|
|
//++
|
|
//
|
|
// 620 Cache Flushing Routines
|
|
//
|
|
// The 620 has seperate instruction and data caches of 32 KB each.
|
|
// Line size = Block size = 64 bytes.
|
|
//
|
|
//
|
|
//
|
|
// HalpSweepDcache620
|
|
//
|
|
// Sweep the entire data cache. This is accomplished by loading
|
|
// the cache with data corresponding to a known address range and
|
|
// then ensuring that each block in the cache is not dirty.
|
|
//
|
|
// As in the 601 case, we use the Hashed Page Table for the data
|
|
// in an effort to minimize performance lost by force feeding the
|
|
// cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
|
|
LEAF_ENTRY(HalpSweepDcache620)
|
|
|
|
li r.4, DCB620 // size of cache in cache blocks
|
|
hsd620:
|
|
mfsdr1 r.3 // fill the D cache from memory
|
|
// allocated to the hashed page
|
|
// table (it's something useful).
|
|
mtctr r.4
|
|
DISABLE_INTERRUPTS(r.10,r.11)
|
|
sync
|
|
oris r.3, r.3, 0x8000 // get VA of hashed page table
|
|
subi r.5, r.3, DCBSZ620 // dec addr prior to inc
|
|
hsd620.ld:
|
|
lbzu r.8, DCBSZ620(r.5)
|
|
bdnz hsd620.ld
|
|
ENABLE_INTERRUPTS(r.10)
|
|
|
|
LEAF_EXIT(HalpSweepDcache620)
|
|
|
|
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepIcache620
|
|
//
|
|
// Sweep the entire instruction cache. This routine is functionally
|
|
// identical to the 604 version except that on the 620 the bit in HID0
|
|
// (coincidentally the *same* bit) is called Instruction Cache Edge
|
|
// Flash Invalidate (ICEFI).
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalpSweepIcache620)
|
|
|
|
mfspr r.3, HID0 // 620, use Instruction
|
|
ori r.3, r.3, H0_620_ICEFI // Cache Edge Flash Invalidate
|
|
isync
|
|
mtspr HID0, r.3 // invalidate I-Cache
|
|
|
|
LEAF_EXIT(HalpSweepIcache620)
|
|
|
|
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepIcacheRange620
|
|
//
|
|
// Remove a range of instructions from the instruction cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// r.3 Start address
|
|
// r.4 Length (in bytes)
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalpSweepIcacheRange620)
|
|
|
|
rlwinm r.5, r.3, 0, DCBSZ620-1 // isolate offset in start block
|
|
addi r.4, r.4, DCBSZ620-1 // bump range by block sz - 1
|
|
add r.4, r.4, r.5 // add start block offset
|
|
srwi r.4, r.4, DCBSZL2620 // number of blocks
|
|
mtctr r.4
|
|
hsir620.fl:
|
|
icbi 0, r.3 // invalidate block in I cache
|
|
addi r.3, r.3, DCBSZ620 // bump address
|
|
bdnz hsir620.fl
|
|
|
|
LEAF_EXIT(HalpSweepIcacheRange620)
|
|
|
|
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepDcacheRange620
|
|
//
|
|
// Force data in a given address range to memory.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// r.3 Start address
|
|
// r.4 Length (in bytes)
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalpSweepDcacheRange620)
|
|
|
|
rlwinm r.5, r.3, 0, DCBSZ620-1 // isolate offset in start block
|
|
addi r.4, r.4, DCBSZ620-1 // bump range by block sz - 1
|
|
add r.4, r.4, r.5 // add start block offset
|
|
srwi r.4, r.4, DCBSZL2620 // number of blocks
|
|
mtctr r.4
|
|
sync
|
|
hsdr620.fl:
|
|
dcbst 0, r.3 // flush block
|
|
addi r.3, r.3, DCBSZ620 // bump address
|
|
bdnz hsdr620.fl
|
|
|
|
LEAF_EXIT(HalpSweepDcacheRange620)
|
|
|
|
|
|
//++
|
|
//
|
|
// HalpSweepPhysicalRangeInBothCaches
|
|
//
|
|
// Force data in a given PHYSICAL address range to memory and
|
|
// invalidate from the block in the instruction cache.
|
|
//
|
|
// This implementation assumes a block size of 32 bytes. It
|
|
// will still work on the 620.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// r.3 Start physical PAGE number.
|
|
// r.4 Starting offset within page. Cache block ALIGNED.
|
|
// r.5 Length (in bytes)
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
.set PAGE_SHIFT, 12
|
|
|
|
|
|
LEAF_ENTRY(HalpSweepPhysicalRangeInBothCaches)
|
|
|
|
//
|
|
// Starting physical address = (PageNumber << PAGE_SHIFT) | Offset
|
|
//
|
|
|
|
rlwimi r.4, r.3, PAGE_SHIFT, 0xfffff000
|
|
|
|
addi r.5, r.5, 31 // bump length by block size - 1
|
|
srwi r.5, r.5, 5 // get number of blocks
|
|
mflr r.0 // save return address
|
|
mtctr r.5 // set loop count
|
|
|
|
//
|
|
// Interrupts MUST be disabled for the duration of this function as
|
|
// we use srr0 and srr1 which will be destroyed by any exception or
|
|
// interrupt.
|
|
//
|
|
|
|
DISABLE_INTERRUPTS(r.12,r.11) // r.11 <- disabled MSR
|
|
// r.12 <- previous MSR
|
|
//
|
|
// Find ourselves in memory. This is needed as we must disable
|
|
// both instruction and data translation. We do this while
|
|
// interrupts are disabled only to try to avoid changing the
|
|
// Link Register when an unwind might/could occur.
|
|
//
|
|
// The HAL is known to be in KSEG0 so its physical address is
|
|
// its effective address with the top bit stripped off.
|
|
//
|
|
|
|
bl hspribc
|
|
hspribc:
|
|
|
|
mflr r.6 // r.6 <- &hspribc
|
|
rlwinm r.6, r.6, 0, 0x7fffffff // r.6 &= 0x7fffffff
|
|
addi r.6, r.6, hspribc.real - hspribc
|
|
// r.6 = real &hspribc.real
|
|
|
|
sync // ensure all previous loads and
|
|
// stores are complete.
|
|
|
|
mtsrr0 r.6 // address in real space
|
|
|
|
rlwinm r.11, r.11, 0, ~0x30 // turn off Data and Instr relocation
|
|
mtsrr1 r.11
|
|
rfi // leap to next instruction
|
|
|
|
hspribc.real:
|
|
mtsrr0 r.0 // set return address
|
|
mtsrr1 r.12 // set old MSR value
|
|
|
|
hspribc.loop:
|
|
dcbst 0, r.4 // flush data block to memory
|
|
icbi 0, r.4 // invalidate i-cache
|
|
addi r.4, r.4, 32 // point to next block
|
|
bdnz hspribc.loop // jif more to do
|
|
|
|
sync // ensure all translations complete
|
|
isync // don't even *think* about getting
|
|
// ahead.
|
|
rfi // return to caller and translated
|
|
// mode
|
|
|
|
DUMMY_EXIT(HalpSweepPhysicalRangeInBothCaches)
|
|
|
|
//++
|
|
//
|
|
// HalpSweepPhysicalIcacheRange
|
|
//
|
|
// Invalidate a given PHYSICAL address range from the instruction
|
|
// cache.
|
|
//
|
|
// This implementation assumes a block size of 32 bytes. It
|
|
// will still work on the 620.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// r.3 Start physical PAGE number.
|
|
// r.4 Starting offset within page. Cache block ALIGNED.
|
|
// r.5 Length (in bytes)
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
|
|
LEAF_ENTRY(HalpSweepPhysicalIcacheRange)
|
|
|
|
//
|
|
// Starting physical address = (PageNumber << PAGE_SHIFT) | Offset
|
|
//
|
|
|
|
rlwimi r.4, r.3, PAGE_SHIFT, 0xfffff000
|
|
|
|
addi r.5, r.5, 31 // bump length by block size - 1
|
|
srwi r.5, r.5, 5 // get number of blocks
|
|
mflr r.0 // save return address
|
|
mtctr r.5 // set loop count
|
|
|
|
//
|
|
// Interrupts MUST be disabled for the duration of this function as
|
|
// we use srr0 and srr1 which will be destroyed by any exception or
|
|
// interrupt.
|
|
//
|
|
|
|
DISABLE_INTERRUPTS(r.12,r.11) // r.11 <- disabled MSR
|
|
// r.12 <- previous MSR
|
|
//
|
|
// Find ourselves in memory. This is needed as we must disable
|
|
// both instruction and data translation. We do this while
|
|
// interrupts are disabled only to try to avoid changing the
|
|
// Link Register when an unwind might/could occur.
|
|
//
|
|
// The HAL is known to be in KSEG0 so its physical address is
|
|
// its effective address with the top bit stripped off.
|
|
//
|
|
|
|
bl hspir
|
|
hspir:
|
|
|
|
mflr r.6 // r.6 <- &hspribc
|
|
rlwinm r.6, r.6, 0, 0x7fffffff // r.6 &= 0x7fffffff
|
|
addi r.6, r.6, hspir.real - hspir
|
|
// r.6 = real &hspribc.real
|
|
|
|
sync // ensure all previous loads and
|
|
// stores are complete.
|
|
|
|
mtsrr0 r.6 // address in real space
|
|
|
|
//
|
|
// N.B. It may not be required that Data Relocation be disabled here.
|
|
// I can't tell from my Arch spec if ICBI works on a Data or
|
|
// Instruction address. I believe it is probably a Data
|
|
// address even though it would be sensible for it to be an
|
|
// instruction address,....
|
|
//
|
|
|
|
rlwinm r.11, r.11, 0, ~0x30 // turn off Data and Instr relocation
|
|
mtsrr1 r.11
|
|
rfi // leap to next instruction
|
|
|
|
hspir.real:
|
|
mtsrr0 r.0 // set return address
|
|
mtsrr1 r.12 // set old MSR value
|
|
|
|
hspir.loop:
|
|
icbi 0, r.4 // invalidate i-cache
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addi r.4, r.4, 32 // point to next block
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bdnz hspir.loop // jif more to do
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|
|
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sync // ensure all translations complete
|
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isync // don't even *think* about getting
|
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// ahead.
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rfi // return to caller and translated
|
|
// mode
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|
DUMMY_EXIT(HalpSweepPhysicalIcacheRange)
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