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823 lines
19 KiB
823 lines
19 KiB
/*++
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Copyright (c) 1992, 1993 Digital Equipment Corporation
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Module Name:
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ev4cache.c
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Abstract:
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This file contains the routines for managing the caches on machines
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based on the DECchip 21064 microprocessor.
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EV4 has primary I and D caches of 8KB each, both write-through.
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Any systems based on EV4 are expected to have an external backup cache
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which is write-back, but it is also coherent with all DMA operations. The
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primary caches are shadowed by the backup, and on a write hit, the
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primary data (but not instruction) cache is invalidated.
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Consequently, the routines to flush,sweep,purge,etc the data
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stream are nops on EV4, but the corresponding routines for the
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Istream must ensure that we cannot hit in the primary I cache
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after a DMA operation.
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EV4 has a write buffer which contains 4 32-byte entries, which
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must be flushable before DMA operations. The MB instruction is
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used to accomplish this.
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There is no coloring support on EV4, so Color operations are
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null. Zero page is unsupported because it has no users. Copy
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page is not special because we lack coloring.
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We had to make a philosophical decision about what interfaces to
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support in this file. (Almost) none of the interfaces defined in
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the HAL spec are actually supported in either the i386 or MIPS
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code. The i386 stream has almost no cache support at all. The
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Mips stream has cache support, but most routines also refer to
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coloring. Should we use the Spec'ed interfaces, or the Mips
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interfaces? I have elected the Mips interfaces because they are
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in use, and we are stealing much of the Mips code which expects
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these interfaces. Besides, the only change we might make is to
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remove the coloring arguments, but they may be used on Alpha
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machines at some future date.
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Author:
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Miche Baker-Harvey (miche) 29-May-1992
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Revision History:
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13-Jul-1992 Jeff McLeman (mcleman)
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use HalpMb to do a memory barrier. Also, alter code and use super
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pages to pass to rtl memory routines.
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10-Jul-1992 Jeff McLeman (mcleman)
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use HalpImb to call pal.
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06-Jul-1992 Jeff McLeman (mcleman)
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Move routine KeFlushDcache into this module.
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Use only one memory barrier in the KeFlushWriteBuffer
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routine. This is because the PAL for the EVx will
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make sure the proper write ordering is done in PAL mode.
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--*/
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// Include files
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#include "halp.h"
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VOID
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HalFlushDcache (
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IN BOOLEAN AllProcessors
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);
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//
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// Cache and write buffer flush functions.
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//
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VOID
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HalChangeColorPage (
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IN PVOID NewColor,
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IN PVOID OldColor,
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IN ULONG PageFrame
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)
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/*++
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Routine Description:
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This function changes the color of a page if the old and new colors
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do not match. DECchip 21064-based machines do not have page coloring, and
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therefore, this function performs no operation.
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Arguments:
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NewColor - Supplies the page aligned virtual address of the
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new color of the page to change.
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OldColor - Supplies the page aligned virtual address of the
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old color of the page to change.
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pageFrame - Supplies the page frame number of the page that
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is changed.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalFlushDcachePage (
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IN PVOID Color,
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IN ULONG PageFrame,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function flushes (invalidates) up to a page of data from the
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data cache.
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Arguments:
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Color - Supplies the starting virtual address and color of the
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data that is flushed.
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PageFrame - Supplies the page frame number of the page that
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is flushed.
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Length - Supplies the length of the region in the page that is
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flushed.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalFlushIoBuffers (
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IN PMDL Mdl,
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IN BOOLEAN ReadOperation,
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IN BOOLEAN DmaOperation
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)
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/*++
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Routine Description:
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This function flushes the I/O buffer specified by the memory descriptor
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list from the data cache on the current processor.
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Arguments:
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Mdl - Supplies a pointer to a memory descriptor list that describes the
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I/O buffer location.
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ReadOperation - Supplies a boolean value that determines whether the I/O
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operation is a read into memory.
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DmaOperation - Supplies a boolean value that determines whether the I/O
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operation is a DMA operation.
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Return Value:
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None.
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--*/
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{
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ULONG CacheSegment;
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ULONG Length;
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ULONG Offset;
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PULONG PageFrame;
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ULONG Address;
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volatile ULONG i;
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volatile ULONG j;
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if (DmaOperation!=FALSE) {
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HalpMb(); // force all previous writes off chip
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Offset = Mdl->ByteOffset;
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Length = Mdl->ByteCount;
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PageFrame = (PULONG)(Mdl + 1);
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//
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// Export or purge the specified page segments from the data and
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// instruction caches as appropriate.
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//
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do {
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if (Length >= (PAGE_SIZE - Offset)) {
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CacheSegment = PAGE_SIZE - Offset;
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} else {
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CacheSegment = Length;
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}
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
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if (HalpModuleHardwareFlushing) {
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Address = *PageFrame << PAGE_SHIFT;
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if (Address & 0x2000) {
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HalpWriteAbsoluteUlong(0xfffffce9,0x00000010,(Address >> 14) & 0xffff);
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} else {
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HalpWriteAbsoluteUlong(0xfffffce8,0x00000010,(Address >> 14) & 0xffff);
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}
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} else {
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Address = (*PageFrame << PAGE_SHIFT) & 0x001fffff;
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for(i=0;i<PAGE_SIZE;i+=0x40) {
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address+i);
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}
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}
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} else {
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if (HalpModuleHardwareFlushing) {
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Address = *PageFrame << PAGE_SHIFT;
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HalpWriteAbsoluteUlong(0xfffffc03,0x40000004,((Address>>21)&0x1ff)<<8);
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HalpWriteAbsoluteUlong(0xfffffc03,0x00000004,((Address>>13)&0xff)<<9);
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HalpReadAbsoluteUlong(0xfffffc03,0x00000000);
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} else {
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Address = (*PageFrame << PAGE_SHIFT) & 0x0007ffff;
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for(i=0;i<PAGE_SIZE;i+=0x20) {
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address+i);
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}
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for(i=0;i<PAGE_SIZE;i+=0x20) {
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+0x200000+Address+i);
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}
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}
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}
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PageFrame += 1;
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Length -= CacheSegment;
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Offset = 0;
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} while(Length != 0);
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}
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//
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// The Dcache coherency is maintained in hardware. The Icache coherency
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// is maintained by invalidating the istream on page read operations.
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//
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HalpMb(); // synchronize this processors view of memory
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if (ReadOperation) {
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HalpMb(); // not issued until previous mb completes
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//
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// If this is an EV4 or an EV45, then do an IMB
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//
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if (HalpIoArchitectureType != EV5_PROCESSOR_MODULE) {
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if (Mdl->MdlFlags & MDL_IO_PAGE_READ) {
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//
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// The operation is a page read, thus the istream must
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// be flushed.
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//
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HalpImb();
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}
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}
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}
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}
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VOID
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HalpCleanIoBuffers (
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IN PMDL Mdl,
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IN BOOLEAN ReadOperation,
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IN BOOLEAN DmaOperation
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)
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/*++
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Routine Description:
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This function flushes the I/O buffer specified by the memory descriptor
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list from the data cache on the current processor.
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Arguments:
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Mdl - Supplies a pointer to a memory descriptor list that describes the
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I/O buffer location.
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ReadOperation - Supplies a boolean value that determines whether the I/O
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operation is a read into memory.
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DmaOperation - Supplies a boolean value that determines whether the I/O
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operation is a DMA operation.
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Return Value:
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None.
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--*/
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{
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ULONG CacheSegment;
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ULONG Length;
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ULONG Offset;
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PULONG PageFrame;
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ULONG Address;
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volatile ULONG i;
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volatile ULONG j;
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// //
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// // If this is an EV4 or an EV45, then do nothing on the backend of DMA operations
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// //
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//
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// if (HalpIoArchitectureType != EV5_PROCESSOR_MODULE) {
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// return;
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// }
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if (DmaOperation!=FALSE) {
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HalpMb(); // force all previous writes off chip
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Offset = Mdl->ByteOffset;
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Length = Mdl->ByteCount;
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PageFrame = (PULONG)(Mdl + 1);
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//
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// Export or purge the specified page segments from the data and
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// instruction caches as appropriate.
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//
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do {
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if (Length >= (PAGE_SIZE - Offset)) {
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CacheSegment = PAGE_SIZE - Offset;
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} else {
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CacheSegment = Length;
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}
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
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if (HalpModuleHardwareFlushing) {
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Address = *PageFrame << PAGE_SHIFT;
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if (Address & 0x2000) {
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HalpWriteAbsoluteUlong(0xfffffce9,0x00000010,(Address >> 14) & 0xffff);
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} else {
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HalpWriteAbsoluteUlong(0xfffffce8,0x00000010,(Address >> 14) & 0xffff);
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}
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} else {
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Address = (*PageFrame << PAGE_SHIFT) & 0x001fffff;
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for(i=0;i<PAGE_SIZE;i+=0x40) {
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address+i);
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}
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}
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} else {
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if (HalpModuleHardwareFlushing) {
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Address = *PageFrame << PAGE_SHIFT;
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HalpWriteAbsoluteUlong(0xfffffc03,0x40000004,((Address>>21)&0x1ff)<<8);
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HalpWriteAbsoluteUlong(0xfffffc03,0x00000004,((Address>>13)&0xff)<<9);
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HalpReadAbsoluteUlong(0xfffffc03,0x00000000);
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} else {
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Address = (*PageFrame << PAGE_SHIFT) & 0x0007ffff;
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for(i=0;i<PAGE_SIZE;i+=0x20) {
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address+i);
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}
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for(i=0;i<PAGE_SIZE;i+=0x20) {
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+0x200000+Address+i);
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}
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}
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}
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PageFrame += 1;
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Length -= CacheSegment;
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Offset = 0;
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} while(Length != 0);
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}
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//
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// The Dcache coherency is maintained in hardware. The Icache coherency
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// is maintained by invalidating the istream on page read operations.
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//
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HalpMb(); // synchronize this processors view of memory
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if (ReadOperation) {
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HalpMb(); // not issued until previous mb completes
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if (Mdl->MdlFlags & MDL_IO_PAGE_READ) {
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//
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// The operation is a page read, thus the istream must
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// be flushed.
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//
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HalpImb();
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}
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}
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}
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VOID
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HalpGoodCleanIoBuffers (
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IN PMDL Mdl,
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IN BOOLEAN ReadOperation,
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IN BOOLEAN DmaOperation
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)
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/*++
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Routine Description:
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|
|
|
This function flushes the I/O buffer specified by the memory descriptor
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list from the data cache on the current processor.
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Arguments:
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Mdl - Supplies a pointer to a memory descriptor list that describes the
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I/O buffer location.
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|
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ReadOperation - Supplies a boolean value that determines whether the I/O
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|
operation is a read into memory.
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DmaOperation - Supplies a boolean value that determines whether the I/O
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operation is a DMA operation.
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Return Value:
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None.
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--*/
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{
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ULONG CacheSegment;
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ULONG Length;
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ULONG Offset;
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PULONG PageFrame;
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ULONG Address;
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volatile ULONG i;
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volatile ULONG j;
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if (DmaOperation!=FALSE) {
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HalpMb(); // force all previous writes off chip
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Offset = Mdl->ByteOffset;
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Length = Mdl->ByteCount;
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PageFrame = (PULONG)(Mdl + 1);
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//
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// Export or purge the specified page segments from the data and
|
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// instruction caches as appropriate.
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//
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do {
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if (Length >= (PAGE_SIZE - Offset)) {
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CacheSegment = PAGE_SIZE - Offset;
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} else {
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CacheSegment = Length;
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}
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
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Address = ((*PageFrame << PAGE_SHIFT) + Offset) & 0x001fffc0;
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address);
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Address = ((*PageFrame << PAGE_SHIFT) + Offset + 0x40) & 0x001fffc0;
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address);
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Address = ((*PageFrame << PAGE_SHIFT) + CacheSegment - 1) & 0x001fffc0;
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address);
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} else {
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Address = ((*PageFrame << PAGE_SHIFT) + Offset) & 0x000fffe0;
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address);
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Address = ((*PageFrame << PAGE_SHIFT) + CacheSegment - 1) & 0x000fffe0;
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j = *(volatile ULONG *)((ULONG)HalpCacheFlushBase+Address);
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}
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PageFrame += 1;
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Length -= CacheSegment;
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Offset = 0;
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} while(Length != 0);
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}
|
|
|
|
//
|
|
// The Dcache coherency is maintained in hardware. The Icache coherency
|
|
// is maintained by invalidating the istream on page read operations.
|
|
//
|
|
HalpMb(); // synchronize this processors view of memory
|
|
if (ReadOperation) {
|
|
HalpMb(); // not issued until previous mb completes
|
|
if (Mdl->MdlFlags & MDL_IO_PAGE_READ) {
|
|
|
|
//
|
|
// The operation is a page read, thus the istream must
|
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// be flushed.
|
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//
|
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HalpImb();
|
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}
|
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}
|
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}
|
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|
|
|
|
|
|
VOID
|
|
HalPurgeDcachePage (
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IN PVOID Color,
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IN ULONG PageFrame,
|
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IN ULONG Length
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)
|
|
/*++
|
|
Routine Description:
|
|
|
|
This function purges (invalidates) up to a page of data from the
|
|
data cache.
|
|
|
|
Arguments:
|
|
|
|
Color - Supplies the starting virtual address and color of the
|
|
data that is purged.
|
|
|
|
PageFrame - Supplies the page frame number of the page that
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|
is purged.
|
|
|
|
Length - Supplies the length of the region in the page that is
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purged.
|
|
|
|
Return Value:
|
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|
|
None.
|
|
|
|
--*/
|
|
{
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return;
|
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}
|
|
|
|
|
|
VOID
|
|
HalPurgeIcachePage (
|
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IN PVOID Color,
|
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IN ULONG PageFrame,
|
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IN ULONG Length
|
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)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function purges (invalidates) up to a page fo data from the
|
|
instruction cache.
|
|
|
|
Arguments:
|
|
|
|
Color - Supplies the starting virtual address and color of the
|
|
data that is purged.
|
|
|
|
PageFrame - Supplies the page frame number of the page that
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|
is purged.
|
|
|
|
Length - Supplies the length of the region in the page that is
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purged.
|
|
|
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Return Value:
|
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|
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None.
|
|
|
|
--*/
|
|
{
|
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//
|
|
// The call to HalpImb calls PAL to flush the Icache, which ensures that
|
|
// any stale hits will be invalidated
|
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//
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HalpImb;
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}
|
|
|
|
VOID
|
|
HalSweepDcache (
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function sweeps (invalidates) the entire data cache.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
HalSweepDcacheRange (
|
|
IN PVOID BaseAddress,
|
|
IN ULONG Length
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function flushes the specified range of addresses from the data
|
|
cache on the current processor.
|
|
|
|
Arguments:
|
|
|
|
BaseAddress - Supplies the starting physical address of a range of
|
|
physical addresses that are to be flushed from the data cache.
|
|
|
|
Length - Supplies the length of the range of physical addresses
|
|
that are to be flushed from the data cache.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
HalSweepIcache (
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function sweeps (invalidates) the entire instruction cache.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
//
|
|
// The call to HalpImb calls PAL to flush the Icache, which ensures that
|
|
// any stale hits will be invalidated
|
|
//
|
|
HalpImb;
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
HalSweepIcacheRange (
|
|
IN PVOID BaseAddress,
|
|
IN ULONG Length
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function flushes the specified range of addresses from the
|
|
instruction cache on the current processor.
|
|
|
|
Arguments:
|
|
|
|
BaseAddress - Supplies the starting physical address of a range of
|
|
physical addresses that are to be flushed from the instruction cache.
|
|
|
|
Length - Supplies the length of the range of physical addresses
|
|
that are to be flushed from the instruction cache.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
//
|
|
// The call to HalpImb calls PAL to flush the Icache, which ensures that
|
|
// any stale hits will be invalidated
|
|
//
|
|
HalpImb;
|
|
|
|
}
|
|
|
|
VOID
|
|
KeFlushWriteBuffer (
|
|
VOID
|
|
)
|
|
|
|
{
|
|
//
|
|
// We flush the write buffer by doing a series of memory
|
|
// barrier operations. It still isn't clear if we need
|
|
// to do two/four of them to flush the buffer, or if one
|
|
// to order the writes is suffcient
|
|
//
|
|
|
|
HalpMb;
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
KeFlushDcache (
|
|
IN BOOLEAN AllProcessors,
|
|
IN PVOID BaseAddress OPTIONAL,
|
|
IN ULONG Length
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function flushes the data cache on all processors that are currently
|
|
running threads which are children of the current process or flushes the
|
|
data cache on all processors in the host configuration.
|
|
|
|
Arguments:
|
|
|
|
AllProcessors - Supplies a boolean value that determines which data
|
|
caches are flushed.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
UNREFERENCED_PARAMETER(BaseAddress);
|
|
UNREFERENCED_PARAMETER(Length);
|
|
|
|
HalFlushDcache(AllProcessors);
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
HalFlushDcache (
|
|
IN BOOLEAN AllProcessors
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function flushes the data cache on all processors that are currently
|
|
running threads which are children of the current process or flushes the
|
|
data cache on all processors in the host configuration.
|
|
|
|
Arguments:
|
|
|
|
AllProcessors - Supplies a boolean value that determines which data
|
|
caches are flushed.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
//
|
|
// Sweep (index/writeback/invalidate) the data cache.
|
|
//
|
|
|
|
HalSweepDcache();
|
|
return;
|
|
}
|
|
|
|
ULONG
|
|
HalGetDmaAlignmentRequirement (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function returns the alignment requirements for DMA transfers on
|
|
host system.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
The DMA alignment requirement is returned as the fucntion value.
|
|
|
|
--*/
|
|
|
|
{
|
|
// if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
|
|
// return 0x40;
|
|
// } else {
|
|
// return 0x20;
|
|
// }
|
|
|
|
//
|
|
// Checked builds will not run with an alignment other than 0x08. It generated assertions
|
|
// when buffers are not aligned correctly and this sometimes happens on the ALPHA builds.
|
|
// However, SCSI Tape device will not work unless the alignment value is correct. So,
|
|
// for right now SCSI Tape devices can not be used with a checked build.
|
|
//
|
|
// Free builds do not have the assertions for unaligned buffers, so we can set the
|
|
// alignment value to the systems actual cache line size. This means that SCSI Tape
|
|
// devices will work with a free build and a free HAL.
|
|
//
|
|
|
|
#ifdef DEBUG
|
|
return 0x08;
|
|
#else
|
|
return 0x40;
|
|
#endif
|
|
}
|