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204 lines
8.7 KiB
204 lines
8.7 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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ixphwsup.c
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Abstract:
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This module contains the HalpXxx routines for the NT I/O system that
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are hardware dependent. Were these routines not hardware dependent,
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they would normally reside in the internal.c module.
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Author:
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Michael D. Kinney 30-Apr-1995
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Environment:
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Kernel mode, local to I/O system
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Revision History:
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--*/
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#include "halp.h"
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#define KERNEL_PCI_VGA_VIDEO_ROM (LONGLONG)(0x8000000000000000)
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PLATFORM_RANGE_LIST Gambit20Trebbia13RangeList[] = {
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{ Isa , 0, BusIo, 0, TREB1_GAMBIT_ISA_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Isa , 0, BusMemory, 0, TREB1_GAMBIT_ISA_MEMORY_BASE_PHYSICAL , 0x00000000, 0x00ffffff },
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{ Isa , 1, BusIo, 0, TREB1_GAMBIT_ISA1_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Isa , 1, BusMemory, 0, TREB1_GAMBIT_ISA1_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ Isa , 1, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ Eisa , 0, BusIo, 0, TREB1_GAMBIT_ISA_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Eisa , 0, BusMemory, 0, TREB1_GAMBIT_ISA_MEMORY_BASE_PHYSICAL , 0x00000000, 0xffffffff },
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{ Eisa , 1, BusIo, 0, TREB1_GAMBIT_ISA1_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Eisa , 1, BusMemory, 0, TREB1_GAMBIT_ISA1_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ Eisa , 1, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ PCIBus, 0, BusIo, 0, TREB1_GAMBIT_PCI_IO_BASE_PHYSICAL , 0x00000000, 0xffffffff },
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{ PCIBus, 0, BusMemory, 0, TREB1_GAMBIT_PCI_MEMORY_BASE_PHYSICAL+0x40000000 , 0x40000000, 0xffffffff },
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{ PCIBus, 1, BusIo, 0, TREB1_GAMBIT_PCI_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ PCIBus, 1, BusMemory, 0, TREB1_GAMBIT_PCI_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ PCIBus, 1, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ PCIBus, 1, BusMemory, 0, TREB1_GAMBIT_PCI_MEMORY_BASE_PHYSICAL+0x40000000 , 0x40000000, 0xffffffff },
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{ MaximumInterfaceType, 0, 0, 0, 0 , 0 , 0 }
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};
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PLATFORM_RANGE_LIST Gambit20Trebbia20RangeList[] = {
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{ Isa , 0, BusIo, 0, TREB2_GAMBIT_ISA_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Isa , 0, BusMemory, 0, TREB2_GAMBIT_ISA_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ Isa , 0, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ Isa , 1, BusIo, 0, TREB2_GAMBIT_ISA1_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Isa , 1, BusMemory, 0, TREB2_GAMBIT_ISA1_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ Isa , 1, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ Eisa , 0, BusIo, 0, TREB2_GAMBIT_ISA_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Eisa , 0, BusMemory, 0, TREB2_GAMBIT_ISA_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ Eisa , 0, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ Eisa , 1, BusIo, 0, TREB2_GAMBIT_ISA1_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ Eisa , 1, BusMemory, 0, TREB2_GAMBIT_ISA1_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ Eisa , 1, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ PCIBus, 0, BusIo, 0, TREB2_GAMBIT_PCI_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ PCIBus, 0, BusMemory, 0, TREB2_GAMBIT_PCI_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ PCIBus, 0, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ PCIBus, 0, BusMemory, 0, TREB2_GAMBIT_PCI_MEMORY_BASE_PHYSICAL+0x40000000 , 0x40000000, 0xffffffff },
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{ PCIBus, 1, BusIo, 0, TREB2_GAMBIT_PCI1_IO_BASE_PHYSICAL , 0x00000000, 0x0000ffff },
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{ PCIBus, 1, BusMemory, 0, TREB2_GAMBIT_PCI1_MEMORY_BASE_PHYSICAL+0xa0000 , 0x000a0000, 0x000bffff },
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{ PCIBus, 1, BusMemory, 0, KERNEL_PCI_VGA_VIDEO_ROM , 0x000c0000, 0x000c7fff },
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{ PCIBus, 1, BusMemory, 0, TREB2_GAMBIT_PCI1_MEMORY_BASE_PHYSICAL+0x40000000 , 0x40000000, 0xffffffff },
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{ MaximumInterfaceType, 0, 0, 0, 0 , 0 , 0 }
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};
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BOOLEAN
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HalpTranslateSystemBusAddress(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress
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)
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{
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ULONG i;
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INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType;
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ULONG BusNumber = BusHandler->BusNumber;
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LONGLONG Offset;
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PVOID va = 0; // note, this is used for a placeholder
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//BusAddress.HighPart = 0;
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//DbgPrint("HalTranslateBusAddress(IT=%d,BN=%d,BA=%08x %08x,AS=%d)\n\r",InterfaceType,BusNumber,BusAddress.HighPart,BusAddress.LowPart,*AddressSpace);
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//
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// PCI Bus 0 is different than PCI Bus 1, but all other PCI busses are the same a PCI Bus 1
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//
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if (InterfaceType == PCIBus) {
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switch (HalpMotherboardType) {
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case TREBBIA13 :
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if (BusNumber > 1) {
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BusNumber = 1;
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}
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break;
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case TREBBIA20 :
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if (BusNumber == 0) {
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//
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// There are no resources in PCI Bus #0. It only contains the memory system and bridges.
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//
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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if (BusNumber >= HalpSecondPciBridgeBusNumber) {
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BusNumber = 1;
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} else {
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BusNumber = 0;
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}
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break;
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default :
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//DbgPrint(" Invalid Motherboard Type\n\r");
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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}
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//
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// If the VGA decodes are not enabled on the DEC PCI-PCI bridge associated with this
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// memory range, then fail the translation.
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//
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if (!(HalpVgaDecodeBusNumber & (1<<BusNumber)) &&
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BusAddress.QuadPart < (LONGLONG)0x0000000000100000 &&
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(((ADDRESS_SPACE_TYPE)(*AddressSpace) == BusMemory) ||
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((ADDRESS_SPACE_TYPE)(*AddressSpace) == UserBusMemory) ||
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((ADDRESS_SPACE_TYPE)(*AddressSpace) == KernelPciDenseMemory) ||
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((ADDRESS_SPACE_TYPE)(*AddressSpace) == UserPciDenseMemory) )) {
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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//
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// Search the table for a valid mapping.
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//
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for(i=0;HalpRangeList[i].InterfaceType!=MaximumInterfaceType;i++) {
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if (HalpRangeList[i].InterfaceType == InterfaceType &&
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HalpRangeList[i].BusNumber == BusNumber &&
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HalpRangeList[i].AddressType == (ADDRESS_SPACE_TYPE)(*AddressSpace) &&
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BusAddress.QuadPart >= HalpRangeList[i].Base &&
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BusAddress.QuadPart <= HalpRangeList[i].Limit ) {
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TranslatedAddress->QuadPart = HalpRangeList[i].SystemBase;
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*AddressSpace = HalpRangeList[i].SystemAddressSpace;
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if (TranslatedAddress->QuadPart & KERNEL_PCI_VGA_VIDEO_ROM) {
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TranslatedAddress->QuadPart &= ~KERNEL_PCI_VGA_VIDEO_ROM;
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if (HalpPlatformParameterBlock->FirmwareRevision >= 50) {
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TranslatedAddress->QuadPart += (LONGLONG)HalpPlatformSpecificExtension->PciVideoExpansionRomAddress;
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} else {
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TranslatedAddress->QuadPart += (TREB1_GAMBIT_ISA_MEMORY_BASE_PHYSICAL + (LONGLONG)0xc0000);
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}
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}
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Offset = BusAddress.QuadPart - HalpRangeList[i].Base;
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TranslatedAddress->QuadPart += Offset;
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return(TRUE);
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}
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}
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//
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// A valid mapping was not found.
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//
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*AddressSpace = 0;
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TranslatedAddress->QuadPart = 0;
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return(FALSE);
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}
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