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1038 lines
34 KiB
1038 lines
34 KiB
// TITLE("Cache Flush")
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//++
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//
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// Copyright (c) 1991 Microsoft Corporation
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//
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// Module Name:
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//
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// j4cache.s
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//
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// Abstract:
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//
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// This module implements the code necessary for cache operations on
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// a MIPS R4000.
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//
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// Author:
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//
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// David N. Cutler (davec) 19-Dec-1991
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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//
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//--
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#include "halmips.h"
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//
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// Define cache operations constants.
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//
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#define COLOR_BITS (7 << PAGE_SHIFT) // color bit (R4000 - 8kb cache)
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#define COLOR_MASK (0x7fff) // color mask (R4000 - 8kb cache)
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#define FLUSH_BASE 0xfffe0000 // flush base address
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#define PROTECTION_BITS ((1 << ENTRYLO_V) | (1 << ENTRYLO_D)) //
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SBTTL("Change Color Page")
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//++
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//
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// VOID
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// HalChangeColorPage (
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// IN PVOID NewColor,
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// IN PVOID OldColor,
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// IN ULONG PageFrame
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// )
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//
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// Routine Description:
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//
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// This function changes the color of a page if the old and new colors
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// do not match.
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//
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// The algorithm used to change colors for a page is as follows:
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//
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// 1. Purge (hit/invalidate) the page from the instruction cache
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// using the old color.
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//
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// 2. Purge (hit/invalidate) the page from the data cache using
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// the old color.
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//
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// Arguments:
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//
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// NewColor (a0) - Supplies the page aligned virtual address of the
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// new color of the page to change.
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//
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// OldColor (a1) - Supplies the page aligned virtual address of the
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// old color of the page to change.
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//
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// PageFrame (a2) - Supplies the page frame number of the page that
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// is changed.
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//
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// Return Value:
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//
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// None.
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//
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//--
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.struct 0
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.space 3 * 4 // fill
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CpRa: .space 4 // saved return address
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CpFrameLength: // length of stack frame
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CpA0: .space 4 // (a0)
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CpA1: .space 4 // (a1)
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CpA2: .space 4 // (a2)
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CpA3: .space 4 // (a3)
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NESTED_ENTRY(HalChangeColorPage, CpFrameLength, zero)
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subu sp,sp,CpFrameLength // allocate stack frame
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sw ra,CpRa(sp) // save return address
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PROLOGUE_END
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and a0,a0,COLOR_BITS // isolate new color bits
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and a1,a1,COLOR_BITS // isolate old color bits
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beq a0,a1,10f // if eq, colors match
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sw a1,CpA1(sp) // save old color bits
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sw a2,CpA2(sp) // save page frame
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//
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// Purge the instruction cache using the old page color.
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//
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move a0,a1 // set color value
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move a1,a2 // set page frame number
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li a2,PAGE_SIZE // set length of purge
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jal HalPurgeIcachePage // purge instruction cache page
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//
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// Flush the data cache using the old page color.
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//
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lw a0,CpA1(sp) // get old color bits
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lw a1,CpA2(sp) // get page frame number
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li a2,PAGE_SIZE // set length of purge
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jal HalFlushDcachePage // purge data cache page
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10: lw ra,CpRa(sp) // get return address
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addu sp,sp,CpFrameLength // deallocate stack frame
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j ra // return
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.end HalChangeColorPage
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SBTTL("Flush Data Cache Page")
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//++
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//
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// VOID
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// HalFlushDcachePage (
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// IN PVOID Color,
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// IN ULONG PageFrame,
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// IN ULONG Length
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// )
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//
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// Routine Description:
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//
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// This function flushes (hit/writeback/invalidate) up to a page of data
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// from the data cache.
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//
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// Arguments:
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//
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// Color (a0) - Supplies the starting virtual address and color of the
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// data that is flushed.
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//
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// PageFrame (a1) - Supplies the page frame number of the page that
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// is flushed.
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//
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// Length (a2) - Supplies the length of the region in the page that is
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// flushed.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalFlushDcachePage)
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#if DBG
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lw t0,KeDcacheFlushCount // get address of dcache flush count
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lw t1,0(t0) // increment the count of flushes
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addu t1,t1,1 //
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sw t1,0(t0) // store result
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#endif
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.set noreorder
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.set noat
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lw v0,KiPcr + PcAlignedCachePolicy(zero) // get cache policy
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and a0,a0,COLOR_MASK // isolate color and offset bits
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li t0,FLUSH_BASE // get base flush address
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or t0,t0,a0 // compute color virtual address
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sll t1,a1,ENTRYLO_PFN // shift page frame into position
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or t1,t1,PROTECTION_BITS // merge protection bits
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or t1,t1,v0 // merge cache policy
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and a0,a0,0x1000 // isolate TB entry index
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beql zero,a0,10f // if eq, first entry
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move t2,zero // set second page table entry
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move t2,t1 // set second page table entry
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move t1,zero // set first page table entry
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10: mfc0 t3,wired // get TB entry index
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lw v0,KiPcr + PcSecondLevelDcacheFillSize(zero) // get 2nd fill size
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lw t4,KiPcr + PcFirstLevelDcacheFillSize(zero) // get 1st fill size
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bnel zero,v0,15f // if ne, second level cache present
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move t4,v0 // set flush block size
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.set at
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.set reorder
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//
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// Flush a page from the data cache.
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//
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15: DISABLE_INTERRUPTS(t5) // disable interrupts
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.set noreorder
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.set noat
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mfc0 t6,entryhi // get current PID and VPN2
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srl t7,t0,ENTRYHI_VPN2 // isolate VPN2 of virtual address
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sll t7,t7,ENTRYHI_VPN2 //
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and t6,t6,0xff << ENTRYHI_PID // isolate current PID
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or t7,t7,t6 // merge PID with VPN2 of virtual address
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mtc0 t7,entryhi // set VPN2 and PID for probe
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mtc0 t1,entrylo0 // set first PTE value
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mtc0 t2,entrylo1 // set second PTE value
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mtc0 t3,index // set TB index value
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nop // fill
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tlbwi // write TB entry - 3 cycle hazzard
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subu t6,t4,1 // compute block size minus one
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and t7,t0,t6 // compute offset in block
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addu a2,a2,t6 // round up to next block
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addu a2,a2,t7 //
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nor t6,t6,zero // complement block size minus one
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and a2,a2,t6 // truncate length to even number
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beq zero,a2,30f // if eq, no blocks to flush
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and t8,t0,t6 // compute starting virtual address
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addu t9,t8,a2 // compute ending virtual address
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bne zero,v0,40f // if ne, second level cache present
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subu t9,t9,t4 // compute ending loop address
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//
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// Flush the primary data cache only.
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//
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20: cache HIT_WRITEBACK_INVALIDATE_D,0(t8) // invalidate cache block
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bne t8,t9,20b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address
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.set at
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.set reorder
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30: ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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//
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// Flush the primary and secondary data caches.
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//
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.set noreorder
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.set noat
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40: cache HIT_WRITEBACK_INVALIDATE_SD,0(t8) // invalidate cache block
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bne t8,t9,40b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address
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.set at
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.set reorder
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ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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.end HalFlushDcachePage
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SBTTL("Purge Data Cache Page")
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//++
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//
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// VOID
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// HalPurgeDcachePage (
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// IN PVOID Color,
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// IN ULONG PageFrame,
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// IN ULONG Length
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// )
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//
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// Routine Description:
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//
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// This function purges (hit/invalidate) up to a page of data from the
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// data cache.
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//
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// Arguments:
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//
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// Color (a0) - Supplies the starting virtual address and color of the
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// data that is purged.
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//
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// PageFrame (a1) - Supplies the page frame number of the page that
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// is purged.
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//
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// Length (a2) - Supplies the length of the region in the page that is
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// purged.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalPurgeDcachePage)
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#if DBG
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lw t0,KeDcacheFlushCount // get address of dcache flush count
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lw t1,0(t0) // increment the count of flushes
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addu t1,t1,1 //
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sw t1,0(t0) // store result
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#endif
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.set noreorder
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.set noat
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lw v0,KiPcr + PcAlignedCachePolicy(zero) // get cache policy
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and a0,a0,COLOR_MASK // isolate color bits
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li t0,FLUSH_BASE // get base flush address
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or t0,t0,a0 // compute color virtual address
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sll t1,a1,ENTRYLO_PFN // shift page frame into position
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or t1,t1,PROTECTION_BITS // merge protection bits
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or t1,t1,v0 // merge cache policy
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and a0,a0,0x1000 // isolate TB entry index
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beql zero,a0,10f // if eq, first entry
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move t2,zero // set second page table entry
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move t2,t1 // set second page table entry
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move t1,zero // set first page table entry
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10: mfc0 t3,wired // get TB entry index
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lw v0,KiPcr + PcSecondLevelDcacheFillSize(zero) // get 2nd fill size
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lw t4,KiPcr + PcFirstLevelDcacheFillSize(zero) // get 1st fill size
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bnel zero,v0,15f // if ne, second level cache present
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move t4,v0 // set purge block size
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.set at
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.set reorder
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//
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// Purge data from the data cache.
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//
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15: DISABLE_INTERRUPTS(t5) // disable interrupts
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.set noreorder
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.set noat
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mfc0 t6,entryhi // get current PID and VPN2
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srl t7,t0,ENTRYHI_VPN2 // isolate VPN2 of virtual address
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sll t7,t7,ENTRYHI_VPN2 //
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and t6,t6,0xff << ENTRYHI_PID // isolate current PID
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or t7,t7,t6 // merge PID with VPN2 of virtual address
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mtc0 t7,entryhi // set VPN2 and PID for probe
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mtc0 t1,entrylo0 // set first PTE value
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mtc0 t2,entrylo1 // set second PTE value
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mtc0 t3,index // set TB index value
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nop // fill
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tlbwi // write TB entry - 3 cycle hazzard
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subu t6,t4,1 // compute block size minus one
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and t7,t0,t6 // compute offset in block
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addu a2,a2,t6 // round up to next block
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addu a2,a2,t7 //
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nor t6,t6,zero // complement block size minus one
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and a2,a2,t6 // truncate length to even number
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beq zero,a2,30f // if eq, no blocks to purge
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and t8,t0,t6 // compute starting virtual address
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addu t9,t8,a2 // compute ending virtual address
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bne zero,v0,40f // if ne, second level cache present
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subu t9,t9,t4 // compute ending loop address
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//
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// Purge the primary data cache only.
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//
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20: cache HIT_INVALIDATE_D,0(t8) // invalidate cache block
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bne t8,t9,20b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address
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.set at
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.set reorder
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30: ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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//
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// Purge the primary and secondary data caches.
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//
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.set noreorder
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.set noat
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40: cache HIT_INVALIDATE_SD,0(t8) // invalidate cache block
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bne t8,t9,40b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address
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.set at
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.set reorder
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ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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.end HalPurgeDcachePage
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SBTTL("Purge Instruction Cache Page")
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//++
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//
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// VOID
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// HalPurgeIcachePage (
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// IN PVOID Color,
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// IN ULONG PageFrame,
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// IN ULONG Length
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// )
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//
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// Routine Description:
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//
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// This function purges (hit/invalidate) up to a page fo data from the
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// instruction cache.
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//
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// Arguments:
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//
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// Color (a0) - Supplies the starting virtual address and color of the
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// data that is purged.
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//
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// PageFrame (a1) - Supplies the page frame number of the page that
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// is purged.
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//
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// Length (a2) - Supplies the length of the region in the page that is
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// purged.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalPurgeIcachePage)
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#if DBG
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lw t0,KeIcacheFlushCount // get address of icache flush count
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lw t1,0(t0) // increment the count of flushes
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addu t1,t1,1 //
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sw t1,0(t0) // store result
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#endif
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.set noreorder
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.set noat
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lw v0,KiPcr + PcAlignedCachePolicy(zero) // get cache policy
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and a0,a0,COLOR_MASK // isolate color bits
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li t0,FLUSH_BASE // get base flush address
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or t0,t0,a0 // compute color virtual address
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sll t1,a1,ENTRYLO_PFN // shift page frame into position
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or t1,t1,PROTECTION_BITS // merge protection bits
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or t1,t1,v0 // merge cache policy
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and a0,a0,0x1000 // isolate TB entry index
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beql zero,a0,10f // if eq, first entry
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move t2,zero // set second page table entry
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move t2,t1 // set second page table entry
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move t1,zero // set first page table entry
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10: mfc0 t3,wired // get TB entry index
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lw v0,KiPcr + PcSecondLevelIcacheFillSize(zero) // get 2nd fill size
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lw t4,KiPcr + PcFirstLevelIcacheFillSize(zero) // get 1st fill size
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bnel zero,v0,15f // if ne, second level cache present
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move t4,v0 // set purge block size
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.set at
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.set reorder
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//
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// Purge data from the instruction cache.
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//
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15: DISABLE_INTERRUPTS(t5) // disable interrupts
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.set noreorder
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.set noat
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mfc0 t6,entryhi // get current PID and VPN2
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srl t7,t0,ENTRYHI_VPN2 // isolate VPN2 of virtual address
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sll t7,t7,ENTRYHI_VPN2 //
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and t6,t6,0xff << ENTRYHI_PID // isolate current PID
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or t7,t7,t6 // merge PID with VPN2 of virtual address
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mtc0 t7,entryhi // set VPN2 and PID for probe
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mtc0 t1,entrylo0 // set first PTE value
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mtc0 t2,entrylo1 // set second PTE value
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mtc0 t3,index // set TB index value
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nop // fill
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tlbwi // write TB entry - 3 cycle hazzard
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subu t6,t4,1 // compute block size minus one
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and t7,t0,t6 // compute offset in block
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addu a2,a2,t6 // round up to next block
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addu a2,a2,t7 //
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nor t6,t6,zero // complement block size minus one
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and a2,a2,t6 // truncate length to even number
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beq zero,a2,30f // if eq, no blocks to purge
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and t8,t0,t6 // compute starting virtual address
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addu t9,t8,a2 // compute ending virtual address
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bne zero,v0,40f // if ne, second level cache present
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subu t9,t9,t4 // compute ending loop address
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//
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// Purge the primary instruction cache only.
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//
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20: cache HIT_INVALIDATE_I,0(t8) // invalidate cache block
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bne t8,t9,20b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address
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.set at
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.set reorder
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30: ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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//
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// Purge the primary and secondary instruction caches.
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//
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.set noreorder
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.set noat
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40: cache HIT_INVALIDATE_SI,0(t8) // invalidate cache block
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bne t8,t9,40b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address
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.set at
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.set reorder
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ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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.end HalPurgeIcachePage
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SBTTL("Sweep Data Cache")
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//++
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//
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// VOID
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// HalSweepDcache (
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// VOID
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// )
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//
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|
// Routine Description:
|
|
//
|
|
// This function sweeps (index/writeback/invalidate) the entire data cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalSweepDcache)
|
|
|
|
#if DBG
|
|
|
|
lw t0,KeDcacheFlushCount // get address of dcache flush count
|
|
lw t1,0(t0) // increment the count of flushes
|
|
addu t1,t1,1 //
|
|
sw t1,0(t0) // store result
|
|
|
|
#endif
|
|
|
|
lw t0,KiPcr + PcFirstLevelDcacheSize(zero) // get data cache size
|
|
lw t1,KiPcr + PcFirstLevelDcacheFillSize(zero) // get block size
|
|
li a0,KSEG0_BASE // set starting index value
|
|
addu a1,a0,t0 // compute ending cache address
|
|
subu a1,a1,t1 // compute ending block address
|
|
|
|
//
|
|
// Sweep the primary data cache.
|
|
//
|
|
|
|
.set noreorder
|
|
.set noat
|
|
10: cache INDEX_WRITEBACK_INVALIDATE_D,0(a0) // writeback/invalidate on index
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
nop // fill
|
|
cache INDEX_WRITEBACK_INVALIDATE_D,8192(a0) // writeback/invalidate on index
|
|
|
|
#endif
|
|
|
|
bne a0,a1,10b // if ne, more to invalidate
|
|
addu a0,a0,t1 // compute address of next block
|
|
.set at
|
|
.set reorder
|
|
|
|
lw t0,KiPcr + PcSecondLevelDcacheSize(zero) // get data cache size
|
|
lw t1,KiPcr + PcSecondLevelDcacheFillSize(zero) // get block size
|
|
beq zero,t1,30f // if eq, no second level cache
|
|
li a0,KSEG0_BASE // set starting index value
|
|
addu a1,a0,t0 // compute ending cache address
|
|
subu a1,a1,t1 // compute ending block address
|
|
|
|
//
|
|
// Sweep the secondary data cache.
|
|
//
|
|
|
|
.set noreorder
|
|
.set noat
|
|
20: cache INDEX_WRITEBACK_INVALIDATE_SD,0(a0) // writeback/invalidate on index
|
|
bne a0,a1,20b // if ne, more to invalidate
|
|
addu a0,a0,t1 // compute address of next block
|
|
.set at
|
|
.set reorder
|
|
|
|
30: j ra // return
|
|
|
|
.end HalSweepDcache
|
|
|
|
SBTTL("Sweep Data Cache Range")
|
|
//++
|
|
//
|
|
// VOID
|
|
// HalSweepDcacheRange (
|
|
// IN PVOID BaseAddress,
|
|
// IN ULONG Length
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// This function sweeps (index/writeback/invalidate) the specified range
|
|
// of virtual addresses from the primary data cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// BaseAddress (a0) - Supplies the base address of the range that is swept
|
|
// from the data cache.
|
|
//
|
|
// Length (a1) - Supplies the length of the range that is swept from the
|
|
// data cache.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalSweepDcacheRange)
|
|
|
|
#if DBG
|
|
|
|
lw t0,KeDcacheFlushCount // get address of dcache flush count
|
|
lw t1,0(t0) // increment the count of flushes
|
|
addu t1,t1,1 //
|
|
sw t1,0(t0) // store result conditionally
|
|
|
|
#endif
|
|
|
|
and a0,a0,COLOR_MASK // isolate color and offset bits
|
|
or a0,a0,KSEG0_BASE // convert to physical address
|
|
lw t0,KiPcr + PcFirstLevelDcacheFillSize(zero) // get block size
|
|
addu a1,a0,a1 // compute ending cache address
|
|
subu a1,a1,t0 // compute ending block address
|
|
|
|
//
|
|
// Sweep the primary data cache.
|
|
//
|
|
|
|
.set noreorder
|
|
.set noat
|
|
10: cache INDEX_WRITEBACK_INVALIDATE_D,0(a0) // writeback/invalidate on index
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
nop // fill
|
|
cache INDEX_WRITEBACK_INVALIDATE_D,8192(a0) // writeback/invalidate on index
|
|
|
|
#endif
|
|
|
|
bne a0,a1,10b // if ne, more to invalidate
|
|
addu a0,a0,t0 // compute address of next block
|
|
.set at
|
|
.set reorder
|
|
|
|
j ra // return
|
|
|
|
.end HalSweepDcacheRange
|
|
|
|
SBTTL("Sweep Instruction Cache")
|
|
//++
|
|
//
|
|
// VOID
|
|
// HalSweepIcache (
|
|
// VOID
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// This function sweeps (index/invalidate) the entire instruction cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalSweepIcache)
|
|
|
|
#if DBG
|
|
|
|
lw t0,KeIcacheFlushCount // get address of icache flush count
|
|
lw t1,0(t0) // increment the count of flushes
|
|
addu t1,t1,1 //
|
|
sw t1,0(t0) // store result
|
|
|
|
#endif
|
|
|
|
lw t0,KiPcr + PcSecondLevelIcacheSize(zero) // get instruction cache size
|
|
lw t1,KiPcr + PcSecondLevelIcacheFillSize(zero) // get fill size
|
|
beq zero,t1,20f // if eq, no second level cache
|
|
li a0,KSEG0_BASE // set starting index value
|
|
addu a1,a0,t0 // compute ending cache address
|
|
subu a1,a1,t1 // compute ending block address
|
|
|
|
//
|
|
// Sweep the secondary instruction cache.
|
|
//
|
|
|
|
.set noreorder
|
|
.set noat
|
|
10: cache INDEX_INVALIDATE_SI,0(a0) // invalidate cache line
|
|
bne a0,a1,10b // if ne, more to invalidate
|
|
addu a0,a0,t1 // compute address of next block
|
|
.set at
|
|
.set reorder
|
|
|
|
20: lw t0,KiPcr + PcFirstLevelIcacheSize(zero) // get instruction cache size
|
|
lw t1,KiPcr + PcFirstLevelIcacheFillSize(zero) // get fill size
|
|
li a0,KSEG0_BASE // set starting index value
|
|
addu a1,a0,t0 // compute ending cache address
|
|
subu a1,a1,t1 // compute ending block address
|
|
|
|
//
|
|
// Sweep the primary instruction cache.
|
|
//
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
DISABLE_INTERRUPTS(t0) // disable interrupts
|
|
|
|
#endif
|
|
|
|
.set noreorder
|
|
.set noat
|
|
30: cache INDEX_INVALIDATE_I,0(a0) // invalidate cache line
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
nop // fill
|
|
cache INDEX_INVALIDATE_I,8192(a0) // writeback/invalidate on index
|
|
|
|
#endif
|
|
|
|
bne a0,a1,30b // if ne, more to invalidate
|
|
addu a0,a0,t1 // compute address of next block
|
|
.set at
|
|
.set reorder
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
ENABLE_INTERRUPTS(t0) // enable interrupts
|
|
|
|
#endif
|
|
|
|
j ra // return
|
|
|
|
.end HalSweepIcache
|
|
|
|
SBTTL("Sweep Instruction Cache Range")
|
|
//++
|
|
//
|
|
// VOID
|
|
// HalSweepIcacheRange (
|
|
// IN PVOID BaseAddress,
|
|
// IN ULONG Length
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// This function sweeps (index/invalidate) the specified range of addresses
|
|
// from the instruction cache.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// BaseAddress (a0) - Supplies the base address of the range that is swept
|
|
// from the instruction cache.
|
|
//
|
|
// Length (a1) - Supplies the length of the range that is swept from the
|
|
// instruction cache.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
LEAF_ENTRY(HalSweepIcacheRange)
|
|
|
|
#if DBG
|
|
|
|
lw t0,KeIcacheFlushCount // get address of icache flush count
|
|
lw t1,0(t0) // increment the count of flushes
|
|
addu t1,t1,1 //
|
|
sw t1,0(t0) // store result
|
|
|
|
#endif
|
|
|
|
and a0,a0,COLOR_MASK // isolate color and offset bits
|
|
or a0,a0,KSEG0_BASE // convert to physical address
|
|
lw t0,KiPcr + PcFirstLevelIcacheFillSize(zero) // get fill size
|
|
addu a1,a0,a1 // compute ending cache address
|
|
subu a1,a1,t0 // compute ending block address
|
|
|
|
//
|
|
// Sweep the primary instruction cache.
|
|
//
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
DISABLE_INTERRUPTS(t1) // disable interrupts
|
|
|
|
#endif
|
|
|
|
.set noreorder
|
|
.set noat
|
|
10: cache INDEX_INVALIDATE_I,0(a0) // invalidate cache line
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
nop // fill
|
|
cache INDEX_INVALIDATE_I,8192(a0) // writeback/invalidate on index
|
|
|
|
#endif
|
|
|
|
bne a0,a1,10b // if ne, more to invalidate
|
|
addu a0,a0,t0 // compute address of next block
|
|
.set at
|
|
.set reorder
|
|
|
|
#if defined(_MIPS_R4600)
|
|
|
|
ENABLE_INTERRUPTS(t1) // enable interrupts
|
|
|
|
#endif
|
|
|
|
j ra // return
|
|
|
|
.end HalSweepIcacheRange
|
|
|
|
SBTTL("Zero Page")
|
|
//++
|
|
//
|
|
// VOID
|
|
// HalZeroPage (
|
|
// IN PVOID NewColor,
|
|
// IN PVOID OldColor,
|
|
// IN ULONG PageFrame
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// This function zeros a page of memory.
|
|
//
|
|
// The algorithm used to zero a page is as follows:
|
|
//
|
|
// 1. Purge (hit/invalidate) the page from the instruction cache
|
|
// using the old color iff the old color is not the same as
|
|
// the new color.
|
|
//
|
|
// 2. Purge (hit/invalidate) the page from the data cache using
|
|
// the old color iff the old color is not the same as the new
|
|
// color.
|
|
//
|
|
// 3. Create (create/dirty/exclusive) the page in the data cache
|
|
// using the new color.
|
|
//
|
|
// 4. Write zeros to the page using the new color.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// NewColor (a0) - Supplies the page aligned virtual address of the
|
|
// new color of the page that is zeroed.
|
|
//
|
|
// OldColor (a1) - Supplies the page aligned virtual address of the
|
|
// old color of the page that is zeroed.
|
|
//
|
|
// PageFrame (a2) - Supplies the page frame number of the page that
|
|
// is zeroed.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
.struct 0
|
|
.space 3 * 4 // fill
|
|
ZpRa: .space 4 // saved return address
|
|
ZpFrameLength: // length of stack frame
|
|
ZpA0: .space 4 // (a0)
|
|
ZpA1: .space 4 // (a1)
|
|
ZpA2: .space 4 // (a2)
|
|
ZpA3: .space 4 // (a3)
|
|
|
|
NESTED_ENTRY(HalZeroPage, ZpFrameLength, zero)
|
|
|
|
subu sp,sp,ZpFrameLength // allocate stack frame
|
|
sw ra,ZpRa(sp) // save return address
|
|
|
|
PROLOGUE_END
|
|
|
|
and a0,a0,COLOR_BITS // isolate new color bits
|
|
and a1,a1,COLOR_BITS // isolate old color bits
|
|
sw a0,ZpA0(sp) // save new color bits
|
|
sw a2,ZpA2(sp) // save page frame
|
|
|
|
//
|
|
// If the old page color is not equal to the new page color, then change
|
|
// the color of the page.
|
|
//
|
|
|
|
beq a0,a1,10f // if eq, colors match
|
|
jal KeChangeColorPage // chagne page color
|
|
|
|
//
|
|
// Create dirty exclusive cache blocks and zero the data.
|
|
//
|
|
|
|
10: lw a3,ZpA0(sp) // get new color bits
|
|
lw a1,ZpA2(sp) // get page frame number
|
|
|
|
.set noreorder
|
|
.set noat
|
|
lw v0,KiPcr + PcAlignedCachePolicy(zero) // get cache polciy
|
|
li t0,FLUSH_BASE // get base flush address
|
|
or t0,t0,a3 // compute new color virtual address
|
|
sll t1,a1,ENTRYLO_PFN // shift page frame into position
|
|
or t1,t1,PROTECTION_BITS // merge protection bits
|
|
or t1,t1,v0 // merge cache policy
|
|
and a3,a3,0x1000 // isolate TB entry index
|
|
beql zero,a3,20f // if eq, first entry
|
|
move t2,zero // set second page table entry
|
|
move t2,t1 // set second page table entry
|
|
move t1,zero // set first page table entry
|
|
20: mfc0 t3,wired // get TB entry index
|
|
lw t4,KiPcr + PcFirstLevelDcacheFillSize(zero) // get 1st fill size
|
|
lw v0,KiPcr + PcSecondLevelDcacheFillSize(zero) // get 2nd fill size
|
|
.set at
|
|
.set reorder
|
|
|
|
DISABLE_INTERRUPTS(t5) // disable interrupts
|
|
|
|
.set noreorder
|
|
.set noat
|
|
mfc0 t6,entryhi // get current PID and VPN2
|
|
srl t7,t0,ENTRYHI_VPN2 // isolate VPN2 of virtual address
|
|
sll t7,t7,ENTRYHI_VPN2 //
|
|
and t6,t6,0xff << ENTRYHI_PID // isolate current PID
|
|
or t7,t7,t6 // merge PID with VPN2 of virtual address
|
|
mtc0 t7,entryhi // set VPN2 and PID for probe
|
|
mtc0 t1,entrylo0 // set first PTE value
|
|
mtc0 t2,entrylo1 // set second PTE value
|
|
mtc0 t3,index // set TB index value
|
|
nop // fill
|
|
tlbwi // write TB entry - 3 cycle hazzard
|
|
addu t9,t0,PAGE_SIZE // compute ending address of block
|
|
dmtc1 zero,f0 // set write pattern
|
|
bne zero,v0,50f // if ne, second level cache present
|
|
and t8,t4,0x10 // test if 16-byte cache block
|
|
|
|
//
|
|
// Zero page in primary data cache only.
|
|
//
|
|
|
|
#if defined(_DUO_)
|
|
|
|
30: sdc1 f0,0(t0) // zero 64-byte block
|
|
sdc1 f0,8(t0) //
|
|
sdc1 f0,16(t0) //
|
|
sdc1 f0,24(t0) //
|
|
sdc1 f0,32(t0) //
|
|
sdc1 f0,40(t0) //
|
|
sdc1 f0,48(t0) //
|
|
addu t0,t0,64 // advance to next 64-byte block
|
|
bne t0,t9,30b // if ne, more to zero
|
|
sdc1 f0,-8(t0) //
|
|
|
|
#else
|
|
|
|
30: cache CREATE_DIRTY_EXCLUSIVE_D,0(t0) // create cache block
|
|
addu t0,t0,t4 // compute next block address
|
|
bne zero,t8,40f // if ne, 16-byte cache line
|
|
sdc1 f0,-16(t0) //
|
|
sdc1 f0,-24(t0) // zero 16 bytes
|
|
sdc1 f0,-32(t0) //
|
|
40: bne t0,t9,30b // if ne, more blocks to zero
|
|
sdc1 f0,-8(t0) // zero 16 bytes
|
|
|
|
#endif
|
|
|
|
.set at
|
|
.set reorder
|
|
|
|
ENABLE_INTERRUPTS(t5) // enable interrupts
|
|
|
|
lw ra,ZpRa(sp) // get return address
|
|
addu sp,sp,ZpFrameLength // deallocate stack frame
|
|
j ra // return
|
|
|
|
//
|
|
// Zero page in primary and secondary data caches.
|
|
//
|
|
|
|
.set noreorder
|
|
.set noat
|
|
|
|
#if defined(_DUO_)
|
|
|
|
50: sdc1 f0,0(t0) // zero 64-byte block
|
|
sdc1 f0,8(t0) //
|
|
sdc1 f0,16(t0) //
|
|
sdc1 f0,24(t0) //
|
|
sdc1 f0,32(t0) //
|
|
sdc1 f0,40(t0) //
|
|
sdc1 f0,48(t0) //
|
|
addu t0,t0,64 // advance to next 64-byte block
|
|
bne t0,t9,50b // if ne, more to zero
|
|
sdc1 f0,-8(t0) //
|
|
|
|
#else
|
|
|
|
50: cache CREATE_DIRTY_EXCLUSIVE_SD,0(t0) // create secondary cache block
|
|
addu v1,v0,t0 // compute ending primary block address
|
|
60: addu t0,t0,t4 // compute next block address
|
|
bne zero,t8,70f // if ne, 16-byte primary cache line
|
|
sdc1 f0,-16(t0) //
|
|
sdc1 f0,-24(t0) // zero 16 bytes
|
|
sdc1 f0,-32(t0) //
|
|
70: bne t0,v1,60b // if ne, more primary blocks to zero
|
|
sdc1 f0,-8(t0) // zero 16 bytes
|
|
bne t0,t9,50b // if ne, more secondary blocks to zero
|
|
nop // fill
|
|
|
|
#endif
|
|
|
|
.set at
|
|
.set reorder
|
|
|
|
ENABLE_INTERRUPTS(t5) // enable interrupts
|
|
|
|
lw ra,ZpRa(sp) // get return address
|
|
addu sp,sp,ZpFrameLength // deallocate stack frame
|
|
j ra // return
|
|
|
|
.end HalZeroPage
|